Honored Contributor I
03-18-2016 11:19 PM
We're considering using Arria V or 10 SOC to interface a CPU to an ONFI 4.0 compliant NAND. The particular NAND that must be supported has 1024 pages/block (arria max is 512) and page size 16384 (plus ECC bits) (arria is up to 8KBytes).Is there any possibility of mating these devices, or no? We could consider "wasting" space in the blocks or pages because it's capacity is much more than we need.... Reason for having this issue: We are new to using NAND flash; we like the Arria because we would not have to ceritify IP, which is an issue in our industry (com'l Aerospace). Thanks for any comments on this!