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Hi (sorry for my "Quetions")
I'm building a multiprocessor system with the requirement that it should contain 2 cpu’s, and communicate in some form trough a dual-port memory (school assignment). I’m using a Stratix Development Kit (1S10) and Quartus II we. 4.2 sp1 with NiosII evaluation kit. My questions are: 1: Can I use the flash device for program memory for both cpu’s? Would this cause collisions or is this managed by the Avalon bus? (I wanted to use on-chip memory but I believe it’s not enough ram-blocks available to support both cpu’s with ROM and RAM + the dualport ram-block) 2: The same as above: Can both cpu’s share the SDRAM block by assigning them to use different address-blocks? 3: How do I address the interrupt-ports on the NIOS II cpu in c-code? (I want cpu_0 to be able to send interrupts to cpu_1…) Any help/comments would be appreciated! Thanks StianLink Copied
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Hello, here are some answers.
1) You can have both using the Flash memory but I don't recommend it (see answer 2) 2) SDRAM is relatively fast so I would target your code to it. Now the tricky part, yes you can have both target the SDRAM but you have to be careful with memory allocation (especially the heap and stack). 3) ........ probably easiest to make a single bit PIO for each processor that you write to which generates the interupt (that's going to be very little logic). Then you would just tie interupt line to the opposite processor (I'm guessing you want the interupt to tell the other processor to look at the DP RAM). Here's my suggestion: Using answer 3 and using SDRAM ram for one CPU and a single 64kB onchip memory for the other may get you by. This is the simplest way that I can think of doing this. If this doesn't sound like a good enough solution maybe someone else here can think of something else. If you have more questions for me drop me an email since my viewing of the forum is off and on these days. Cheers, and good-luck http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif
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