RAM and FLASH shared bus don't worked

[Altera_Forum]

Hello everyone, 

 I developped my own custom board which have MT48LC16M16 (Micron SDRam), S29AL032D (Spansion Flash) and Cyclone III EP3C25. RAM and FLASH share data and address bus. The Flash memory is 16 bit data mode. Now i can program the flash via JTAG module but the problem is that the program (just blinked led) does'nt worked after programming the flash (already reset), this program work well with RAM!  Does anyone can help me or any ideas?  Thanks very much and best regards!

[Altera_Forum]

Hi , 

 When you program Flash or RAM , what bridge ip core are you using to access Flash or Ram . I have done it before and the Altera provides a core that creates a bridge during configuration to burn flash . I think you need to disable RAM or take the SDRam out and then try it .

[Altera_Forum]

Hello FPGA_guru011, 

 Thanks for your reply, i'm using pipeline bridge, tri state bridge, cfi and sdram controller core. Please see my attached image!  Thanks very much!

[Altera_Forum]

Hi,  

--- Quote Start ---  Now i can program the flash via JTAG module but the problem is that the program (just blinked led) does'nt worked after programming the flash (already reset), this program work well with ram!  --- Quote End ---   You surely mean the flash that shared address and data bus (S29AL032D (Spansion Flash)), don't you ? Then your FPGA hard design (SOPC + custom logic) is OK.  I see on your attached image that multiple SOPC components have the same base address 0x00000000, but I see no error warning ?!  Do you configure correctly the Spansion flash in SOPC : timings (very important), reset_n, byte enable, chip select, write_n..., dynamic/native, data bus with.... ?  Note : SOPC will be discontinued and replaced by Qsys. But for you, keep with SOPC.

[Altera_Forum]

Hi mmTsuchi, 

 Thanks for your reply, my flash and ram shared address and data bus (my flash is 16 bit mode); i configure flash timing is 40-160-40, byte enable to 3.3V via 4k7 resistor, i checked data and address in shared signals of tristate bridge. the address 0x00000000 that you saw is control by pipeline bridge, so i have that address and the pipeline bridges have different address.  I programmed flash with flash programmer, i wonder that there is different booting method from 8 bit flash and 16 bit flash.  Do you have any suggestions? Thanks in advance

[Altera_Forum]

Hi, 

 Are you declare your flash as a cfi (Common Flash Interface) in SOPC ? 80% YES  I don't know Pipeline Bridge. I could suggest you to connect as this :   Nios Cpu <--> Tristate Bridge <--> Flash |-> SRAM   If you are not afraid with Nios2-terminal, you can "debug" with command-line executable like  nios2-terminal, nios2-download, nios2-flash-programmer...  8bit or 16bit Flash are transparent for booting method. It just tell SOPC how to handle the flash. Transparent for software.  Try something like nios2-flash-programmer --debug (read help files) andtell us what you get. Regards.

[Altera_Forum]

Hi, 

 I change the hardware configuration like you said:   Nios Cpu <-->Tristate Bridge<-->CFI. the flash and sdram share a common bus 16 bit data and address  |-> SDRam Controller  I use the nios-command-shell, the results are in the attached file. Please see it!  When I used this configuration working with on-chip memory ram, the program work fine. Then I change booting to SDRam, it can't run. I think that Flash can't boot to RAM or something wrong in declaration. Is there problem when i shared 16 bit common data?  I'm looking foward to hear you soon! Thanks very much!

[Altera_Forum]

The flash seems to be correctly identified by CFI. 

 I suggest you to assign the flash to address 0x00000000, and assign reset_vector to 0x00000000 in Nios II Cpu configuration. Have you tried to download to flash via command line ? to see if successful flash programming.  Don't be disturbed with 8bits or 16bits for software.  Do you correctly configure SDRAM controller.

[Altera_Forum]

Hi mmTsuchi, 

 Thanks for your reply, I'm working on the project with Judau and config for this project. About hardware:  + I'm using the sdram 8Mbyte of Micron and using sdram controller core and check in (Share pins via tristate bridge, Tristate bridge selection i had chossed the tri_state_bridge which handle the cfi_flash). About timing of sdram controller i setting default. + I'm using the cfi_flash S29AL032D of Spainsion and using the CFI controller core. Address width is 21, Data width is 16 because cfi_flash sharing data and address with sdram (limited i/o pin in hardware). About the timing 40-160-40ns. And in the schematic WP#, RY/BY# pull up 4k7 resitor to 3V3, and pin 47 BYTE# (F_MODE) control by FPGA (assign F_MODE = 1'b1  And i had made on chip ram 24KB for testing. The reset_vector using cfi_flash. The exception_vector using sdram. The nios ii config .text, .rodata, .rwdata, heap and stack i setting at sdram.  My problem now is when i set .text, .rodata, .rwdata, heap and stack i setting at on chip ram and programing to cfi_flash complete after reset the LED test blink ok but when i set .text, .rodata, .rwdata, heap and stack i setting at sdram, the nios not working.  Can you help me!  Thanks and Regard!. Q.Cuong.

[Altera_Forum]

Hi, have you succeeded in working with sdram only ? Keep same configuration but download and run from sdram. 

 Put your exception_vector to on-chip RAM (I don't remember the good ways to configure those vector but it is surely explained in an Altera Handbook).  Have you tried to check RAM ? Take diagnostics nios example software and adapt it (just a little work) to your board.