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Hello, i made a custom component in Qsys.
This component has a reset input signal (conduit export) and a reset output signal (Reset Output interface). The reset output signal is connected to the nios_cpu reset_n input all inside the Qsys system. When the FPGA start with on-chip memory initialized all works fine but when i drive low the reset input pin of my component that drive low the reset_n pin of the nios, the nios stop and not reset it-self. I tried different pulse width but nothing works. I don't know if there is some parameters to set in the Reset Output interface of my component to properly reset the nios. I would like to keep the nios in reset state for an arbitrary time.Link Copied
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You need to assert the 'reset_n' signal for a significant period - I think it is sampled once per instruction.
The 'reset out' signal is driver for a single clock (or two?) each time the processor detects 'reset_n'. While 'reset_n' is asserted, the processer starts coming out of reset, reads the first instruction word, then resets itself again before executing it.- Mark as New
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i tried different period for keeping low the reset_n input but when i release this input the nios is always blocked. i think that i will use the cpu_resetrequest and cpu_resettaken IO available in the nios_cpu component.
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Ah - those are the signals I was thinking about!
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Hi , I am facing the same problem . I am new user to Nios , so can anyone please explain how to solve this issue ?
I have a Qsys system with Nios CPU , ON-chip ram and few PIOs . I initialize the on-chip RAM with a .hex file and create the .pof file. Once I burn the .pof inside the FPGA, on-chip RAM gets initialized and the Nios starts running as expected. But when the device is running , if I give a manual reset to the Qsys system with an external switch , the processor goes into a reset state and it stays in reset state even after i de-assert the reset switch. Also, when a power on reset sequence occurs, the processor will execute code correctly. It only mis-behaves when the reset occurs from an external switch input. Both the reset vector and exception vector of the Nios Processor is in the On-Chip RAM- Mark as New
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--- Quote Start --- Hi , I am facing the same problem . I am new user to Nios , so can anyone please explain how to solve this issue ? I have a Qsys system with Nios CPU , ON-chip ram and few PIOs . I initialize the on-chip RAM with a .hex file and create the .pof file. Once I burn the .pof inside the FPGA, on-chip RAM gets initialized and the Nios starts running as expected. But when the device is running , if I give a manual reset to the Qsys system with an external switch , the processor goes into a reset state and it stays in reset state even after i de-assert the reset switch. Also, when a power on reset sequence occurs, the processor will execute code correctly. It only mis-behaves when the reset occurs from an external switch input. Both the reset vector and exception vector of the Nios Processor is in the On-Chip RAM --- Quote End --- Have you implemented a debounce logic/circuit for the switch? Have you managed the cpu_resetrequest and cpu_resettaken IO available in the nios_cpu component?
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