A block outside the Qsys system generates data which can be read from a FIFO. Thus, the exposed interface is q, empty, rdreq. I want to connect Qsys to this design and read the data generated by this block and written into its FIFO.
Since the FIFO is external the Qsys system, I could connect to it via PIO. However, I am sure that a superior method exists to achieve this end. How should this be done?
