Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12435 Discussions

Read Write to DRAM (main memory)

Altera_Forum
Honored Contributor II
1,052 Views

I am just switching from another fpga to altera. 

 

Could you please tell me is this the write way to access main memory. 

 

main_memory = (char *) DDR2_SDRAM_BASEADDR; // base address of main memory can be changed in system.h file 

main_memory1 = (char *) DDR2_SDRAM_BASEADDR+1024; // base address of main memory can be changed in system.h file 

 

for ( x = 0 ; x < 262122 ; x = x +1) 

*(main_memory+x) = *(main_memory1+x); 

 

regards 

UCERD
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
90 Views

This isn't the right way if the "main memory" is also used for your software. The beginning of the memory is generally used for the exception vectors, and if you overwrite those you will crash the system. 

It is a lot safer to allocate a block of memory to use, either by using malloc() to allocate at run time, or by using a static or global table to allocate at compile time.
Altera_Forum
Honored Contributor II
90 Views

 

--- Quote Start ---  

This isn't the right way if the "main memory" is also used for your software. The beginning of the memory is generally used for the exception vectors, and if you overwrite those you will crash the system. 

It is a lot safer to allocate a block of memory to use, either by using malloc() to allocate at run time, or by using a static or global table to allocate at compile time. 

--- Quote End ---  

 

 

Yes you are right but the reason for using directly baseaddress is, I have two DRAM controller on my FPGA board.  

The memory controller (We designed) can access read/write operation in parallel, that is why for comparison we are designing a baseline system (Nios system based) that can access both memories in parallel.
Altera_Forum
Honored Contributor II
90 Views

Well if you are sure that this memory section is never used by other parts of the software, then you can do it this way. If the memory buffer is shared with some hardware (a DMA for example) then remember to flush the cache before the hardware accesses the memory, or use uncached access through alt_remap_uncached()

Reply