Read and write 16 bits device via Avalon

[Altera_Forum]

Hi there, 

I have create a SOPC Builder component to have access to a USB peripheral controller. This USB controller has a 16 bits data bus et one address line (2 addresses: '0' and '1'). My SOPC component use clk, irq, chipselect, read, write, address, readdate and writedate signals from Avalon bus.  For the software driver, I use IOWR_16DIRECT() and IORD_16DIRECT() macro functions from io.h. With this I got following behavior:[list][*]IOWR_16DIRECT(BASE_ADDRESS, 0, 0xffff): write access on address '0' (correct)  [*]IOWR_16DIRECT(BASE_ADDRESS, 1, 0xffff): write acces on address '0' and address '1' (incorrect)  [*]IORD_16DIRECT(BASE_ADDRESS, 0): read access on address '0' and address '1' (incorrect)  [*]IORD_16DIRECT(BASE_ADDRESS, 1): read access on address '0' and address '1' (incorrect) [/list] I changed the READ and WRITE macro to this one: #define IOWR16(ADDRESS, OFFSET, VALUE) *(((volatile unsigned short *)(ADDRESS)) + (OFFSET)) = (VALUE)# define IORD16(ADDRESS, OFFSET)             *(((volatile unsigned short *)(ADDRESS)) + (OFFSET))  Now I got following behavior:[list][*]IOWR16(BASE_ADDRESS, 0, 0xffff): write access on address '0' (correct)  [*]IOWR16(BASE_ADDRESS, 1, 0xffff): write acces on address '1' (correct)  [*]IORD16(BASE_ADDRESS, 0): read access on address '0' and address '1' (incorrect)  [*]IORD16(BASE_ADDRESS, 1): read access on address '0' and address '1' (incorrect) [/list] Any suggestions how I can erase the unwanted read access ?  Regards  Fabrice

[Altera_Forum]

1. Please use "Register (Native/Static addressing)", and IOWR/IORD unless you know the difference about IO*_*Direct and IO* 

 2. Take care of your Timing of USB controller  3. Could you tell us what Interface you using , Avalon slave or Avalon tri-state? As I see "readdata,writedata" , it is Avalon slave, istn't it?  4. How do you connect the A0,A1 of usb to the Nios system?

[Altera_Forum]

Hello mountain8848, 

Here more details about my SOPC Builder component.  1. I was using "Memory" addressing mode, now I switch to "Register".  2. To have correct timing for the USB device, I use a clock @ 36MHz for this SOPC Builder component, this clock is not needed by the USB device, it just need Read, Write and Chipselect signals. Is there another and/or perhaps better way to specify bus timings ?  3. I use Avalon Slave interface. I think it's the best choice, or not ?  4. For the address signals, I carried out serveral tests. First, after reading page 6-26 from Quartus II Handbook, Volume 4, I was thinking that Avalon address signal allways presents a byte address. So I put 3 address line on Avalon side (eg. address(2 downto 0)). address(0) --> Not used because data bus with is 16 bits address(1) --> A0 from USB Device address(2) --> For selection between USB Device and internal registers. But after some tests I saw that address(0) is not Avalon A0 signal but seems to be A1 !  So I change my address bus with on Avalon side to address(1 downto 0). address(0) --> A0 from USB Device address(1) --> For selection between USB Device and internal registers.  Now I use IORD() and IOWR() macros and this configuration seems to work.

[Altera_Forum]

1. 

Yeah, It is.  2. You can specify the Timing of USB in the "avalon slave timing" of "interface" Tab. The time/ cycle you added will implement by your "system clock" in FPGA logic.  3. I think it is the best/only choice, cause it is a "register" device. ( there are regesters in the device) While the memory device, such as SRAM, flash should using "memeory(Dynamic addressing)" interface.  4. " page 6-26 from Quartus II Handbook, Volume 4" talks about "The Avalon tristate address" not the avalon slave. Avalon slave will connects slave's A0 to Nios(master)'s A2..A0 depending on the data-width of your slave. SO what you test is right/normal/successful way.   Do you using "Add HDL files..." to start make your own comoponets? It is also meas: do you write a hdl to add the components?

[Altera_Forum]

Many thanks for your help and advices. 

This helps me very much to create my Avalon interface for my USB device.  Yes I use HDL file to create my component because I need to drive some additionnal pin to control DMA transfers and IRQ acknowlegde. And with the HDL file it is ease to create an internal register and logic to do this.