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Altera_Forum
Honored Contributor I
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Read out uninitialized SRAM m10K from FPGA fabric on Cyclone V SoC

Hi, 

 

Our goal is to read out the uninitialized m10K in cyclone V SoC contents on power up.  

 

First of all, in the internal memory user guide of cyclone V SoC, I only see the output of m10K are reset on power up and we can initialize XX..X on power up in simulation. How about the contents? Are all the contents also reset to 0? Can we skip this reset/initialization? 

 

However, we are not able to see uninitialized SRAM contents from the FPGA fabric. We implement our simple test circuit by:  

(1) on FPGA fabric only, without interface to or from HPS, 

(2) using an M10K block ram as the SRAM, 

(3) in Quartus, checking the "No, leave it blank" and "initialize to XX...X on power up in simulation", or create an initialization file with contents as XX..X, 

(4) configuring using JTAG through on-board USB-blaster II, 

(5) showing each word in M10K on user LED every second. 

 

So I was wondering whether we miss some important steps to bypass the SRAM initialization/reset in order to read out uninitialized SRAM contents. Could you help us by pointing to critical steps/tools/docs?
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