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Altera_Forum
Honored Contributor I
768 Views

Read wait on nios component not working / bus timing problem ?

Hello, 

 

I have made a Nios/qsys VHDL component. 

The component has a read wait of 2 cycles (defined in signals & interfaces in qsys). (See attached JPG) 

 

In the component I implemented for test purposes a shift register and I read the contents of the shift register back with a C program: 

if (avalon_slave_byteenable='1') and (avalon_slave_address="0010") and (avalon_slave_read='1') and (RcvRdreq="0000") then RcvRdreq <="1111"; -- fill shift register at read end if; if (RcvRdreq/="0000") then -- shift shift register if not zero and set value on avalon bus: RcvRdreq <='0' & RcvRdreq(3 downto 1); -- shift register avalon_slave_readdata<="0000" & RcvRdreq; -- put value on bus end if; reading value of bus with C program:  

while (1) { int status; status =IORD_8DIRECT(COMP _BASE,2); printf("Status = %x\n",status); } The result I get in the nios console window is 0x0F. 

 

If I force the value of rcvRdrReq in the VHDL program, the output changes to the appropriate value, so reading of thebus at the right location works properly. 

The fact that i get 0x0F means that the value is read directly after issuing the read request and not after 2 cycles?  

I assume oversaw something but I do not see what ? Please comment.  

Thanks, 

Johi.
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1 Reply
Altera_Forum
Honored Contributor I
35 Views

Solved, 

 

Value of 0xFF is correct. 

Interpretation of timing diagram was the problem. 

 

Best Regards, 

Johi.
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