04-17-2015 08:13 AM
Hello,I'm working on a Cyclone V, and I want to read and write into HPS's registers. i have in qsys: - One Nios II Processor (with on-chip memory, jtag-uart, system id, etc.) - One HPS - (and other components) My Nios II processor act as a master and the HPS as a slave. in nios ii: I use IORD_32DIRECT, IOWR_32DIRECT, etc. in quartus: I watch signals thanks to signaltap (ARADDR, ARREADY, ARVALID, RLAST, RREADY, RVALID, BRESP, RRESP, RDATA, WDATA, etc.) documentation: The document I used for address maps is the following : https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v4.pdf remarks and question: I noticed that I could read/write in SDRAM-ACP registers (0x00000000 to 0xC0000000) and Lightweight H-to-F registers (from 0xFF200000 to 0xFF400000): page 423 of the document. But what I want is to read/write at the address 0xFFC05000 which is the register for I2C1. The responses i get are BRESP and RRESP = 0x3 (which correspond to an error) My question is : do I have something to active/enable if I want to access to these registers?
04-17-2015 09:32 AM
Hello Taz,I found the problem: I had signals AWPROT and ARPROT = 0x2, which means I was in nonsecure access. I made a mask to force the bit 1 of these signals to 0 and now it's ok... Thank you anyway :)