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Honored Contributor I
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Regarding Exception Vector

Hi, this is sundaram from University of Waterloo. I don't understand what exception vector is completely. My understanding goes something like this. Exception Vector is the place where the executable section of the code begins. For Example, the executable code, the read-only data, the read-write data, the heap are all dynamically mapped onto the memory from the exception vector. if this understanding of mine is right, I have a quick question regarding all this. Is there a way to find how much memory each of these regions occupies? 

 

And this question is more important: is there a way to change the exception address for a cpu at run time? or is there a way to find where the Program counter of the cpu currently is?
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Honored Contributor I
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Like any other processor, Nios exception vector address is fixed. It is defined by hardware implementation so that the processor knows where the program counter must move in response to interrupts and any critical event. 

On the other hand code, data, heap and stack placement depends from linker and you can change them at compile time. You can instruct linker to map each memory section in a different memory device: sdram, onchip ram, sram. 

 

You can find out the memory occupation using nios2-elf-size or nios2-elf-objdump with your application .elf file. With objdump you can retrieve the memory mapping of each symbol defined in your code.
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Honored Contributor I
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So this is my question : is there a way to manipulate the .text section for example at run time? Like is it possible to keep the cpu at resetreq while we go on to modify the .text?

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Honored Contributor I
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This is commonly called "boot holding". So yes it is common to hold the processor in reset while you update the software image. Another method is to make a small rom that you jump to while the main memory is being updated by some other host before jumping to the new application. I made one a long time ago that took a bit in from outside the system which would force the processor to jump to it and it only contained one instruction "PC <- PC + 4 - 4" (i.e. keep executing the same instruction). If you update the contents of the memory after the processor has been running you may need to invalidate the cache since old values may be cached still. Cache invalidation is part of the Nios II boot code so if you jump directly to the new main() then you'll be skipping all the initialization code and bad things will happen as a result.

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Honored Contributor I
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Thanks BadOmen. You have always been ma good omen I suppose :-).  

I have a quick question. 

 

Let's assume for the moment that the CPU has no cache and stuff.. I have a scenario. Let's assume that there are two processors - one idle and the other working on a process. let's assume that the processor 1 has been stopped executing its share of code at some point. (Let's assume that the .text, .rodata, .rwdata and heap of both the processors are on the same memory and different offsets). Now, if we copy the individual sections of cpu1 to the corresponding sections of cpu2, and ask the cpu2 to execute the instruction where cpu1 was stopped, will it be able to do that theoretically?
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Honored Contributor I
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That would be difficult since you would have to restore the state of CPU1 in CPU2 (registers, stacks, etc...) This is kinda what operating systems do in SMP mode. There might be an easier way to do something similar to achieve whatever your end goal is. For example if you wrote your code to store off states and restore them and you only transferred the code from one processor to another at places in the code that do the state storing/restoring that would be probably much easier to implement.

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