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Altera_Forum
Honored Contributor I
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SDC File, conflicting create_clock statements in IP

I've created my timing constraints file. I use create_clk to define my system clk off my input pin (appropriately named clk) 

I'm using some Altera IP - the TSE. It creates a separate clock off this same pin, and complains. 

 

Ignored create_clock at eth_std_main_system_ethernet_subsystem_tse_mac_constraints.sdc(155): Incorrect assignment for clock. Source node: clk already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated. 

create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports $CLK] 

 

If I include the "-add" in this statement, the error goes away. The error doesn't go away if I include the -add statement in my original file.... 

 

This implies that the order of how the SDC files are read is important. However, if I change the order in Quartus settings, when I go to test the SDC settings in Timequest, the files don't get read in that order. 

 

I already have a precompilation script that automatically runs that inserts new names for the clocks at the beginning of the file. It seems crazy that I have to resort to this 

 

What is the "correct" way to deal with this? 

 

 

 

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