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Altera_Forum
Honored Contributor I
1,697 Views

SDR SDRAM memory tests

Hello, 

I've designed a board, with 5 separate SDR SDRAM chips, now I've got the PCBs and trying to test the memory reads/writes. 3 of the chips are working fine, however two of them behaves strange. 

 

For memory tests, I've created a small Qsys design with on-chip memory, where I've placed Nios. The CPU runs an example of Altera called Memory test. 

 

Now here's what's happening: 

<----> Nios II Memory Test. <----> This software example tests the memory in your system to assure it is working properly. This test is destructive to the contents of the memory it tests. Assure the memory being tested does not contain the executable or data sections of this code or the exception address of the system. ---------------------------------- Memory Test Main Menu ---------------------------------- a: Test RAM b: Test Flash q: Exit ---------------------------------- Select Choice (a-b): a Base address to start memory test: (i.e. 0x800000) > 0x00 End Address: > 0x7fffff Testing RAM from 0x0 to 0x7FFFFF -Data bus test passed -Address bus test passed -Byte and half-word access test passed -Testing each bit <<-- not a full sentence, crashed here! <----> Nios II Memory Test. <----> This software example tests the memory in your system to assure it is working properly. This test is destructive to the contents of the memory it tests. Assure the memory being tested does not contain the executable or data sections of this code or the exception address of the system. ---------------------------------- Memory Test Main Menu ---------------------------------- a: Test RAM b: Test Flash q: Exit ---------------------------------- Select Choice (a-b):  

 

As You can see, the sentence "-Testing each bit in memory device . . . ." has been cut and the software restarted. I don't understand why is this happening and what could cause such crashes. Sometimes, the data output is cut somewhere else, e.g. in the beginning of tests: "Testing RAM" and then immediate restart. 

 

The system clock is 50MHz 

The SDRAM chip is feeded 50MHz -55deg from the same PLL 

I am pretty sure the connections are OK. 

If I give incorrect clock to the chip, e.g. the same clock, as I give it to memory controller, then it just stops right after memory tests start, giving a result, that memory test failed at bit 0x1.
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4 Replies
Altera_Forum
Honored Contributor I
119 Views

The first thing I can think of is the same as what the first part of the console output states: 

are you sure you have mapped every Nios memory sections into onchip ram? I mean code, data, but also stack, exception/reset vectors and possibly other sections.
Altera_Forum
Honored Contributor I
119 Views

Yep, I've entered BSP parameters and edited linker script pointing all .bss, .reset, etc stuff to on-chip ram. The RAM chip itself is connected only through data bus. Actually, I am not sure what's wrong. The test is simple: when I map pins in pin planner to working chip - test runs fine, when I map pins to non-working chip - it doesn't. Timing problems? 50MHz shouldn't be a big issue.

Altera_Forum
Honored Contributor I
119 Views

Firstly I'd rewrite the JTAG? UART driver to be completely synchronous and/or add enough delay after every \n to ensure the output has drained. 

Otherwise you have NFI when the lockup happens. 

 

Make sure you have code at the reset vector that indicates a reset - not a restart etc.
Altera_Forum
Honored Contributor I
119 Views

Well, it's a simple setup, commonly used for Nios: I've placed reset vector on the very beginning of the on-chip ram and exception vector at the beginning + 0x20. On-chip ram size is 128KB (131072 Bytes)

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