SDRAM Controller unconstrained pins

[Altera_Forum]

Hi, 

I use the DDR & DDR2 SDRAM Controller Compiler (not the high performance one) with Nios CPU in SOPC. The SOPC builder generates constraints scripts which are run when the design is compiled in Quartus and a "In-system timing verification" is generated. When I look at the TimeQuest report, all the SDRAM pins are reported as "unconstrained". Is it correct? do I have to write additional constraints for this interface?

[Altera_Forum]

It's been a while so hopefully I remember how it worked.... 

 The old DDR/DDR2 controller would output a .tcl file which you would run that set a bunch of constraints on the placement of the logic hooked up to the I/O. So fish around in the generated file set and see if you can find that file.  Now these are just placement constraints so these I/O will still be reported as unconstrained. To be honest I can't think of a good way to resolve those warnings because if you add your own constraints you will probably end up negating the placement constraints. The old controller was created long before Timequest was present in Quartus II so if you can upgrade to the high performance controller I would highly recommend doing so. The new controller supports Timequest and is a much better core as well.