Hi,I am attempting (several ways) to use hw/sftw on EPCQ256 with Stratix III as follows. o If I convert the SOF to a JIC and program the EPCQ256 with quartus programmer => then power up SIII configuration fails o If I convert the SOF to a JIC, but selecting "disable EPCS ID check", and program the EPCQ256 with quartus programmer => then power up configuration works every time o If I try to program the hardware configuration, and also the software, with the flash programmer GUI => then power up SIII configuration fails o Next I try the following steps o sof2flash o elf2flash o concatenate the sof and elf files together o use object copy to convert this flash file to hex o use quartus convert programming file to convert this hex file to a jic file (specifying "disable EPCS ID check") o program EPCQ256 with quartus => then power up SIII configuration fails o Next I try these steps o elf2flash o use object copy to convert this elf flash file to hex o use quartus convert programming file to convert sof file (first) and software hex file (second) to a jic file (specifying "disable EPCS ID check") o program EPCQ256 with quartus => then power up SIII configuration is successful => software does not start => I see in gdb that boot copier expects first 32 bytes of hdw image to be 0xff => I see that the last of these bytes is not 0xff => the boot copier tries to load the elf out of the sof image => when that this isnt going well it traps itself in an infinite loop So ... perhaps in quartus 13.1 the SIII boot copier relies on some specialized magic in sof2flash, but I dont know how to disable the EPCS ID check anywhere in the sof2elf command line, and perhaps that is the root issue. Another possibility is that QSYS generate has elected to provide the wrong version of the boot copier for my SIII/EPCQ256 situation (my EPCS is in a qsys subsystem)? Any suggestions? PS: design is fully constrained, and meets timing Thanks, Jeff
When I program with the jic made from sof and sftw hex (which successfullyconfigures the SIII), and then read back (using nios2-flash-programmer -R) from the EPCQ256, I see this. S1230000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF56A5 S12300207FEF6FEF6FEFCF5F5B1F5B5B1B1B1F3F1F1F3FBFBF5F3F3FBFBF9FBF3F9F3F3F90 S1230040BF3F57B7171F5F57CB76FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79 S1230060FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9C S1230080FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7C S12300A0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5C S12300C0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C S12300E0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1C S1230100FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB Whereas, if one looks at the flash file generated by sof2flash one sees this. S016000046434D5F546F705F4C6576656C2E666C617368EE S32500000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA S32500000020567FEF6FEF6FEFCF5F5B1F5B5B1B1B1F3F1F1F3FBFBF5F3F3FBFBF9FBF3F9F3F77 S325000000403FBF3F57B7171F5F57CB76FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF37 S32500000060FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A S32500000080FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A So comparing these two maybe I can see some differences in the first two lines. JIC read back: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF56A5 7FEF6FEF6FEFCF5F5B1F5B5B1B1B1F3F1F1F3FBFBF5F3F3FBFBF9FBF3F9F3F3F90 sof2flash: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA 567FEF6FEF6FEFCF5F5B1F5B5B1B1B1F3F1F1F3FBFBF5F3F3FBFBF9FBF3F9F3F77 And maybe there are some bytes inserted in the stream that are different. JIC read back: 56A5 sof2flash: FFFA56
Looking closer at srec (.flash) format it becomes clear that the last two nibbles are a checksum and that the primary difference is that bytes 0-31 are 0xff with sof2flash output, wheras only bytes 0 through 30 are 0xff in the JIC read back as a flash file.
When I patch the Altera boot loader as follows, placing the modified code in on chip ram, and change the nios2 to boot from this on chip ram then it boots off of the EPCQ256 jit image configured with the hdw followed by software.Index: boot/boot_loader_epcs_bits_sii_siii_ciii.S =================================================================== --- boot/boot_loader_epcs_bits_sii_siii_ciii.S (revision 359) +++ boot/boot_loader_epcs_bits_sii_siii_ciii.S (working copy) @@ -525,7 +525,7 @@ // // Search until we expect configuration data to start - movi r_findp_count, 32 + movi r_findp_count, 31 // What we'll accept until we see the pattern movi r_findp_temp, 0xFF @@ -549,15 +549,15 @@ // // The configuration bitstream length is encoded in a particular bit of a // run of bytes. Total length field is 32 bits, which goes from CB Option - // bits 86..55 corresponding to bit of byte to byte (for the most + // bits 86..55 corresponding to bit of byte to byte (for the most // significant 7 bits) followed by the range of bits made up of bit of - // bytes[72..48]. + // bytes[71..47]. // // The note about EPCS bit reversal still applies (so we're really looking // at bits and , respectively. // - // First, loop through bits in bytes [48..72] - LSB of the length first + // First, loop through bits in bytes [47..71] - LSB of the length first // Number of bytes we'll traverse to get the length movi r_findp_count, 25 @@ -565,7 +565,7 @@ movi r_findp_temp, 0 // Close & re-open EPCS where we will start extracting the length - movi r_flash_ptr, 48 + movi r_flash_ptr, 47 nextpc return_address_less_4 br sub_epcs_close nextpc return_address_less_4 @@ -596,13 +596,13 @@ bne r_findp_count, r_zero, fp_assemble_configuration_length // We've assembled 25 bits of the length; 7 to go. - // We're gonna look at bit of byte[33..39]. + // We're gonna look at bit of byte[32..38]. // Number of bytes we'll traverse to get the length movi r_findp_count, 7 - // Close & re-open EPCS at byte 33 - movi r_flash_ptr, 33 + // Close & re-open EPCS at byte 32 + movi r_flash_ptr, 32 nextpc return_address_less_4 br sub_epcs_close nextpc return_address_less_4