SMP support in the Linux System with Nios2

[Altera_Forum]

Hello all! 

 I'm studying a multicore Nios2 system for my thesis. After trying with several applications to understand the function of mutex and mailbox, I decided to use also an operative system. Reading some threads, I've downloaded the uClinux to try to build a system with two cpus (cpu1 and cpu2). I'd want to use the cpu1 with linux and the cpu2 as support for some parallel applications. Due several issues, I understand (please correct me if I'm saying something wrong) that uClinux does not support smp. Is there a method to build a system with two cores wich include an operative system on one of them? If yes, can you tell me if there is a tutorial anywhere? I know that the linux kernel 2.6.x supports the smp, so I also thought to try to build a kernel image for the Nios, but in the menuconfig (of a linux kernel, not uClinux) I'm not able to find the architecture for a Nios2.  Hoping I didn't say too much nonsense, thank you in advance!  Antonio

[Altera_Forum]

Linux for NIOS does not support SMP and due to the not exiting cache synchronization features of the NIOS CPU (and some other issues) it's impossible to create a decent SMP system with this CPU.  

 Of course you can use multiple independent CPUs that don't share memory regions on an Avalon bus. You need to use dedicated "hardware" to allow communication between the CPUs (e.g. FiFos or explicitly not-cached memory regions protected by additional hardware semaphores)   -Michael

[Altera_Forum]

--- Quote Start ---  I've downloaded the uClinux to try to build a system with two cpus (cpu1 and cpu2). I'd want to use the cpu1 with linux and the cpu2 as support for some parallel applications. Due several issues, I understand (please correct me if I'm saying something wrong) that uClinux does not support smp. Is there a method to build a system with two cores wich include an operative system on one of them? If yes, can you tell me if there is a tutorial anywhere?  --- Quote End ---   This application is not SMP. You can run Linux on one of the cores, it's pretty straight-forward. If you have two processors you just need to make sure sopc-create-header-files and nios2-download use the right processor.  If you name your cpu "Linux_cpu": sopc-create-header-files --module Linux_cpu --single custom_fpga.h and nios2-download -g zImage --instance 1 && nios2-terminal  IIRC you can only have a JTAG UART on one of the processors.  The two processors will each have their own reset address and everything so you need to set them up separately to boot their software e.g. from flash. There's an example on Altera's site that explains how to have one processor load the software into the other's memory and reset it, if that's what you want to do.

[Altera_Forum]

>> IIRC you can only have a JTAG UART on one of the processors. 

 Really ?   I seem to remember that I once found the the JTAG UARTs are numbered and when accessing them by by a terminal window you can optionally give a number to denote whch one you want to see. So you can use multiple terminal windows.   -Michael

[Altera_Forum]

Thanks to all for your replies. 

   --- Quote Start ---  If you name your cpu "Linux_cpu": Code: sopc-create-header-files --module Linux_cpu --single custom_fpga.h and Code: nios2-download -g zImage --instance 1 && nios2-terminal  --- Quote End ---    I've already try with those commands, specifying the --module and the --istance of the cpu on which I prepared my linux kernel, and all works perfect except for my purpose. In fact if I try to run a "cat /proc/cpuinfo" it display only infos about the cpu on which I put my kernel.  The purpose of my study is about the porting, upon an fpga multicore system,of an application that at this time run on a general purpose linux machine ; so I need that an operative system (on one Nios2 cpu) can "see" others cores to use some MPI application.  Thanks,   Antonio

[Altera_Forum]

--- Quote Start ---  Thanks to all for your replies.    I've already try with those commands, specifying the --module and the --istance of the cpu on which I prepared my linux kernel, and all works perfect except for my purpose. In fact if I try to run a "cat /proc/cpuinfo" it display only infos about the cpu on which I put my kernel.  The purpose of my study is about the porting, upon an fpga multicore system,of an application that at this time run on a general purpose linux machine ; so I need that an operative system (on one Nios2 cpu) can "see" others cores to use some MPI application.  Thanks,   Antonio  --- Quote End ---    The operating system will not know about the existence of the other CPU. Can you explain a bit what you are trying to do?

[Altera_Forum]

--- Quote Start ---  >> IIRC you can only have a JTAG UART on one of the processors.  Really ?   I seem to remember that I once found the the JTAG UARTs are numbered and when accessing them by by a terminal window you can optionally give a number to denote whch one you want to see. So you can use multiple terminal windows.   -Michael  --- Quote End ---   I don't know, I never actually tried it.

[Altera_Forum]

--- Quote Start ---  The operating system will not know about the existence of the other CPU. Can you explain a bit what you are trying to do?  --- Quote End ---    Hi! The idea is to verify if there are computational improvements using a multicore system instead of a single core. At this moment the software that I would to transfer on the fpga is running on a pc under linux. The reason of the multicore system is because the load that this software treats is variable, so I would to build an application that is able to understand the data load and that it's able to divide the computational calculation on several softcore cpus (maybe using the MPI library).  Antonio

[Altera_Forum]

>> maybe using the MPI library 

 Obviously nit possible with NIOS  -Michael

[Altera_Forum]

How to manage the other cpus in the linux on one of the Nios cpu?

[Altera_Forum]

--- Quote Start ---  How to manage the other cpus in the linux on one of the Nios cpu?  --- Quote End ---   As they share the avalon bus, the CPUs can communicate via same, e.g using a memory region (beware of cache issues !!) and/or via dedicated hardware (FiFos, Mutex, ...).   -Michael