Hi, I prepare design with NiosII and SPI bus with 4 slaves. All slaves have different SPI standard (I mean clock polarity and clock phase to data). Is there a possibility to change SPI setup by the software? Is there some recommendation how to chnage clock signal in FPGA (between Nios and IO pin?). Or i need 4 SPI interfaces in Nios design and then connect bus together (I hope, you understand me.)?Thanks, Milan
The possibility to change SPI setup in software depends on the SPI core you are using.IIRC the standard SPI core available in Qsys doesn't allow this, but other 3rd party cores do. In such cases it's a matter or writing proper values in the control registers. The main problem can be with the slaves which would decode in the wrong way spi data and you could mess up everything. Probably you can manage this with slave select lines, provided that your slave doesn't complain about 'abnormal' spi traffic when its SS is deasserted.
Understand. The 3rd party cores, you wrote, are they free or must I buy them somewhere? Do you have an idea aboyt HW consumption (standard SPI core with 5 slaves consumes about 56 ALMs)?
Search on opencores.org for free SPI cores.HW resource usage is little affected by the number of slaves (you only need one extra CS line for each new slave). It is dependent on the features you need to implement. For example a fixed sclk frequency core would consume far less resources compared to a core with programmable frequency .
No. On opencores you usually find the bare-metal core and you need to integrate it into your system.In general you need: 1. build a HDL wrapper to interface to Avalon bus; most of opencores devices are based on wishbone bone which can be interfaced to Avalon in a quite straightforward way 2. create the Qsys custom component 3. write the HAL driver: this can be as simple as raw IOWRs/IORDs at device base address + reg