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SPI slave mode - CS is getting glitch (CYCLONII:EP2C8F256C7)

Altera_Forum
Honored Contributor II
794 Views

Hello, 

 

I created a block using Qsys - SPI (3 wire serial) which has been configured as slave: mode0 (polarity& phase), data8bit, msb first. 

The clock of spi block is 48Mhz. 

 

I send information through external MCU with SPI Master configuration same as FPGA, in the frequency of 5.5 Mhz (tried to descend to the 350Khz and it did not solve the glitch) 

ChipSelect configurated as No pull (tried pull up/down and the problem is still appears).  

 

the problem: 

I receive glitch in ChipSelect that causes obstruction of information received. Here are the photos:  

http://www.alteraforum.com/forum/attachment.php?attachmentid=12803&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12804&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12805&stc=1
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