Hi all,we have a custom board with an SRAM chip (same model is on the DE2 board). We are using this one because we could not get the SDRAM running. Well, we are also having problems with the SRAM. We can run the memory test from nios II in on chip memory, all addresses are written and read correctly. However, when the time comes to put our code in the SRAM the elf file download process fails and it does not work!! We have lost several days with this and we don't have any idea about what can possibly be wrong, because the memory test actually works fine (signals have been verified with signal tap). We also don't know how to debug. Might be something in the programming process? How can we check that? Please any helpful hint will be kindly appreciatted!!
The memory test includes DMA transactions...."if" your system has a standard Avalon DMA in it. The DMA portion will hit the memory much faster back-to-back than any of the other tests. You should not skip this portion/feature of the memory tests..You may be dealing with a situation where Nios II read master transactions are successful, but instruction master "fetches" are failing. You could also just try adding a few read or write wait states to see if that helps to get the Nios II executing from the offchip memory. You can tune it later on. Cheers, slacker
Thanks for your answer Slacker,I don't think we have any DMA in our nios system. We have been messing around with the waitstates: we changed the tcl file provided by altera, regenerated the core, look at the read and write ops and those times were increased according to what we set. When we tried again to program it did not work. However, we did one last change; we incremented the setup and hold times (they were set to 0 by default) to at least 1 cycle through the tcl file. And now it works! It looks like that was what was causing the issue, which would make sense. I hope this can help other users, too. Thanks a lot for pointing us in the right direction!