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Valued Contributor III

SRAM on Third Party Board Woes

Hello All, 


I bought a Cyclone EP1C12Q240C6 Badge Development Board, made by Axiom Manufacturing, from Future Electronics last year. I am trying to interface to the SRAM for the board.  

The Website for the board is: (

The Login information is: 

User: futurecyclone 

Password: sopcnios 


Below is a link to the schematic for the Future Electronics board: (


The board has two Cypress CY7C1041CV33 256K x 16 SRAM chips, -12ns speed grade. Here is a link to a webpage about the SRAM: (


The memory appears to be very similar to the IDT71V416S SRAM that comes on the Altera Cyclone 1C20 NIOS Board. The footprint is pretty much the same and read/write control and timing for this SRAM is almost identical to the Cypress SRAM I have. 

Below is a link to the IDT SRAM website: (

Below is the link to the Cypress SRAM data sheet: 

cypress sram (


There is a component in SOPC Builder that is for the IDT SRAM on the 1C20 Board. I do not know what speed grade the IDT SRAM is. Here is the schematic for the 1C20 Board: (

Here is a link to all the Altera NIOS II development board info: (



my question is, is there a way to adapt this idt 71v416s sram component to work with my board? 

one thing that i am confused about it is what to do with the read_n_to_the_ext_ram signal. neither the idt chip nor the cypress chip have a read signal (re_n), they only have a write enable signal (we_n). there are the ce_n and and oe_n signals, which are used to control the read and write cycles.<#EMO_DIR#>/sad.gif  



I looked at many posts and saw that some people were editing class.ptf files. I could not find the class.ptf file for this component. 


I also followed the SRAM SOPC Builder Example (Building Memory Subsystems Using SOPC Builder) in the Quartus II version 5.1 Handbook, but it left me confused. Here is a link to the guide (the part I am talking about is toward the end.) : (


First, it too had the read_n_to_the_ext_ram signal, which I don’t know what to do with. Second, I got an error that said the Tristate Bridge needed a clock. Third, the wizard only had 4 fields for configuring the timing for the access cycles. I do not understand how those 4 fields can configure all that is necessary for having the CE, BHE, BLE, and OE signals asserted at the proper times to execute the timing for the read cycles and the write cycles (granted, there is more than one way to perform each type of the cycles).  


My board’s clock runs at 50 MHz. The SRAM is a -12ns device. I imagine that there needs to be wait states because the SRAM is faster than the system clock. I don’t know of a way to have a faster clock for the SOPC builder component to run the SRAM signals off, utilizing the 12ns capacity for speed, so again, it looks like wait time is needed. And it looks like I am starting to ramble.<#EMO_DIR#>/ohmy.gif  


could anyone provide clarification on how this custom component interface works, if this is the right approach to take?  

do i need to build my own special sram controller, not following the aforementioned sopc builder guide?<#EMO_DIR#>/huh.gif  


Sorry that this is such a long post. I am new to the forum, and to developing with Altera SOPC Builder and NIOS processors. 


Thank you in advance for any help you are able to offer, or clarification you can make.<#EMO_DIR#>/rolleyes.gif
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