Hello everybody,I have changed the verilog code for the interval timer added in the sopc builder. The problem is that everytime I re-generate the system, my lines are cleared. Is there any mark that the system generation script doesn`t clear? Many thanks ifdm P.D These marks don't work: // <ALTERA_NOTE> CODE INSERTED BETWEEN HERE // AND HERE WILL BE PRESERVED </ALTERA_NOTE>
That is not possible, it would require changes to the source code of the timer so that your modifications would be emitted into the verilog/vhdl it creates. The source for the component is written in an old language that isn't very readable so I wouldn't recommend doing this.You could feed the modified generated verilog through component editor to make a new timer component. The tricky part would be to make it recognized as a timer by the software tools. You can probably grab the driver and software .tcl file from the source directory and hack that up to be matched up with your new hardware. You would also need to add to the hardware .tcl file information like the clock period, timeout period, etc... so that the HAL driver works.