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Honored Contributor I

Share variables and data between Nios2 and HDL prefably VHDL




How do I send data from Nios 2 processor to HDL in quartus. I need to send data such as a variable i.e. a=5; or array[20] to the vhdl side in quartus. How do I set up a shared memory space. I am using the Altera DE3 board. Please explain to me carefully, I have around 4 months of vhdl and fpga experience.  






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4 Replies
Honored Contributor I

Simplest way is through an avalon MM slave.

Honored Contributor I

How would I go about implementing the avalon MM Slave to send data through?

Honored Contributor I

On the HDL side refer to the avalon specification: 


On NIOS side use "IORD" and "IOWR" 

poking through some of the nios example templates will help with learn how to do this
Honored Contributor I



i also would like to know how this works.  


In my project i want to send some control parameters to the Nios processor via the rs232 interface.  

Nios should then store them in some kind of a shared memory location where my custom vhdl logic reads from.  



I read that i could use a DMA or SGDMA Controller but this seems a bit of an overkill since i just want to sent parameters. 

I know the address range of my DDR3 RAM and how to write to a specific address. But i have a understanding problem with  

the reading part. 



I need an avalon slave device which i hook up to the avalon interconnect. 

Could i simply use a FIFO in write/read slave modus? 

If i connect the NIOS instruction and data master with the slave-in port and export the slave-out port to connect it up my logic.  

With C i then write directly to the Fifo buffer and the vhdl logic reads from the buffer directly.(?) 


Since only master-slave connections are allowed my logic to act as a master and initiate the read operations.  

and the vhdl module needs a lot of control functionalities like readdata, read address ? 


Or is it easier to use a onchip memory ram device with dual port access.  

I could write a specific parameter to a specific mem address and through this exact mapping its simple in  

VHDL to extract the parameters. 

But i still have the uncertainty with the slave port to the vhdl module and in general how to set up this shared memory location. 


The more i read about this topic the more i get confused and  

it would be great if you guys could help me  



Thanks in advance