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Shared memory

Honored Contributor I


I would like to make a big (e.g. 8Mbyte) buffer for my core, but also share the same DRAM chip with Nios. Here are my options: 


1) Use SGDMA and allocate memory in software. 

2) Use memory for my core and Nios, but edit linker script to skip first 8MB of memory. 


The first idea would be great, but my packet size is 188 bytes, so to fill 8MB of data I would need a huge list of descriptors. Or there are any other options using SGDMA? 


The second idea would be ok if it is safe to use? I know that I could place .reset in a certain place of RAM, but the .reset vector in the design will be placed in on-chip memory for bootloader to start. 


Since there are DRAM and SRAM chips on almost every Altera devkit, so they use SRAM for Nios and DRAM for specified application. I don't have so much space on the board to fit two memory devices. 


What other options can I have?
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3 Replies
Honored Contributor I

I'm just pondering a similar thing myself, but i don't think i'm too clued in on this subject. 

This may be a stupid point of view and you probably have this sorted but.... (shoot me down if it is): 

i would think you couldn't split the memory like that unless they shared a common controller. since the writes and reads would need to be co-ordinated. 

you would have to do the sgdma control yeah?
Honored Contributor I

SGDMA would solve this by itself, however the descriptor list, which points where to write or read the data, would be very big. You need to write a descriptor for every packet You want to place on the memory.

Honored Contributor I

There shouldn't be any problems 'reserving' a specific (aligned) 8Mb area of DRAM for use by other hardware by editing the linker script. Nothing else should need changing. 

The Avalon switch fabric will arbitrate between the two masters.