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Altera_Forum
Honored Contributor I
776 Views

Sharing access to SDRAM between NIOS and hardware

I want to develop a system where nios would run on and read data from the RAM, but i want to store a constantly updating data on the RAM using hardware. Is is possible to implement such a system on Cyclone II ? Will there be any conflict if both system wants to access the RAM at the same time? Also, if I have to create a memory controller in SoPC builder for NIOS- do i (or can I) access the same controller in my verilog codes, or create another one to interface with the hardware part? 

I am new to FPGA systems, so any hints on where to start, or anything that should be known beforehand to implement such a system without arousing conflict in the RAM will be welcome. 

 

MY TARGET: My project is to build a pretty simple video processing system where I want to get the data from the TV decoder, and do the processing work in the nios system. But getting the data directly using the microprocessor would be inefficient I believe, so I wanted to store the data directly into the ram. 

 

Thank you.
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3 Replies
Altera_Forum
Honored Contributor I
53 Views

Read more about DMA and SGDMA.

Altera_Forum
Honored Contributor I
53 Views

If you put an Avalon MM master interface on your verilog block it can use that to access memory that can be also be accessed from the NIos, the Avalon 'bus' interface logic will hande arbitration between the two masters. 

 

For on-chip memory blocks you can dual-port them between a nios cpu tightly-coupled data block and the avalon bus - this gives the cpu faster access and avoids any issues with the data cache 'interfering' with IO accesses.
Altera_Forum
Honored Contributor I
53 Views

Thanks for the replies. From a quick reading, it seems SGDMA may be the right answer for me.