Sharing data and address between SDRAM and Flash

[Altera_Forum]

Hello, 

 Due to some limitation in the amount of IO pins SDRAM and Flash have to share the same address and data bus. Are there any differences between connecting the Flash to a separate tri-state bus and the shared bus? So is A0 the same A0 in both situations (A0 = least significant address = choose between lower and upper byte)? When connection a 16 bit flash that would mean to connect A1 of the bus to A0 of the flash (AMD flash) because the flash can only be addressed 16 bit wide. As far as I know from the literature that’s the way is should work. What do you think? Is anyone using the same configuration?   Regards, niosIIuser

[Altera_Forum]

I think you should add a tri-state bridge to connect Flash device to Nios Flash componet. And tri-state's A0 is map to byte access.

[Altera_Forum]

Hello mountain8848, 

 That the way I think too. This week the Embedded World starts in Nuremberg (Germany). I try to ask an FAE. The result will be posted here.   Regards, niosIIuser

[Altera_Forum]

Hello, 

 The answers from the Altera guys on the Embedded World haven’t been very satisfactorily. Nobody could say be the use of bit 0 from the address bus when sharing data and address between Flash and SDRAM. The people told me to do a simulation. Now I did the simulation and the answer is: A0 is the byte addressing bit as it was assumed.   Regards, niosIIuser

[Altera_Forum]

NIIUser, 

 You're correct about A0 being the byte addressing bit, for the flash, but the current implementation of the SDRAM controller makes use of all address bits from A0-An, regardless of whether it's in tristate mode or not.  So, if you're in a situation where you have all 16 bit wide devices on the tristate bus, you'd still have to route A0 to the SDRAM. Please keep this in mind if you're implementing this on a board.  Best Regards,  - slacker

[Altera_Forum]

Hello slacker, 

 Thank you for that information. Recapitulating when data and address bus is shared between SDRAM and other tri-state devices the connection of the SDRAM signals doesn’t change (A0 of the SDRAM must be connected with A0 of the external bus) and A0 of the external bus must be used for the other devices on the bus for byte addressing.  When the hardware is ready to start I will post the results here.   Regards, niosIIuser