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Altera_Forum
Honored Contributor I
934 Views

Simple NiosII Design Synthesized away RAM node

Hi, I used to work with Nios II like six months ago with Quartus II v.11. I start to work again two days ago with it, but I can make a simple niosII + PIO to blink some leds. 

 

My problems start at hardware compilation, it only show a lot of warning but this one worries me: 

 

Warning (14285): Synthesized away the following RAM node(s): 

 

If I expand the warning I have a lot of reference to Ram nodes, and I have a lot of entrys in my Connectivity Checks like: 

 

Port Connectivity Checks: "first_nios_system:inst|first_nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" 

 

The design download correctly to the board but when I try to load my C program the process fail because eclipse cant start teh nios II. 

 

Should I be worried for the warnings? maybe its something else? By the way Im working under Ubuntu Linux 11.10 

 

Thanks!
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4 Replies
Altera_Forum
Honored Contributor I
52 Views

Maybe you've forgotten to connect the cpu's data (or instruction) masters to the Avalon 'bus' - in which case the entire cpu might get synthesized away!

Altera_Forum
Honored Contributor I
52 Views

Maybe the reset into the CPU is left disconnected. Quartus II typically drives a 0 into dangling inputs and Nios II uses the reset_n line (so if you don't hook up reset the CPU will get stuck in reset). Take a screenshot of your system and attach it to this post and I'll take a look.

Altera_Forum
Honored Contributor I
52 Views

Hi thanks for your interest. 

 

I just tried agin to build a project and its working! The things that I do diferent are: 

 

1) Im working with a DE0 - nano at my home, at the university I work with a DE2. 

2) I ran eclipse with sudo. 

 

Everything its working properly now, but Im still getting a lot of warnings that iI dont now how to handle, the warnings are in the attachment of this message. 

 

Tomorrow I will try again at the University to replicate the system (image quartus and qsys), if anybody have ideas about the warnings please share with me. 

 

Sorry about my english and I really value your advice Thanks!
Altera_Forum
Honored Contributor I
52 Views

All of those warnings you can ignore except the one about the memory being synthesized away (not sure it's safe to ignore since I don't see the culprit). 

 

One suggestion, hook up the JTAG Debug Module reset to all of the reset inputs in your system so that the external reset or the debugger can trigger a reset. When I download code I normally enable the downloader to reset my system so that I know it'll be in a known state when the code starts executing. 

 

The only other thing that I can think of is did you make sure to assign your clock and PIO signals to I/O? If you didn't assign those Quartus will normally figure out the clock for you and hook it up to an FPGA clock pin (doesn't necessarily mean that clock pin is connected to a valid clock on your board though). The PIO it would just route those signals to wherever it can to improve the timing of your design. I've seen this cause problems for others in the past since having inputs/outputs randomly routed can cause all kinds of nasty stuff to happen. 

 

Also I would hook up the reset pin in your design after you get the code downloading working correctly. I've seen others design themselves into a corner by omitting resets in their design so I would just get into a habit of always including it.
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