I tried without success to simulate a Quartus project which contain a Qsys system and external vhdl component.
I created my Qsys system that contains a Nios II cpu and an interface which export signals to communicate with my vhdl component.
So in my top level entity i have my processors component generated by Qsys connected to the other vhdl component.
I just add all of necessary vhdl component to modelsim, and try to simulate clicking on start simulation and choosing my own testBench.
Under ModelSim, all of my project files compile successfully and simulate, but signals of my processor that correspond to the bus avalon, as its clock or dataRead signal or write signal , are uninitialized.
So I don't find the way to simulate all of the project with modelsim , can someone Help me to do so ? what files have to be added to modelsim project ?
I think some files are missing to simulate the processor's behavior but it doesn't prevent modelsim from compiling.
Thank you for your help.
