SoC FPGA Ethernet Performance

[Altera_Forum]

Hi, 

 I have application that needs to transfer 1 gigabit/s of data generated by the FPGA over Ethernet. FPGA generated data would be written to HPS's DDR3-memory. The data would be transferred over 1G Ethernet via TCP/IP Linux stack. What SoC FPGA-device would be needed to get this performance? Cyclone V or Arria 10?  regards, Joonas

[Altera_Forum]

With DE1-Soc (Cyclone V, 1 Gbps Ethernet) I get 500 MBps of effective datarate with Linux. You have some overhead in different layers when using ethernet. If you are looking for 1 gigabit maybe you have to use 2 ethernet ports.

[Altera_Forum]

Where does this 500 Mbps limitation comes from? From the memory controller's bandwidth, processor's speed or L3 Interconnect's limited bandwidth? If the limiting factor is some of these, I would not expect to get 1 gigabit performance with 2 ethernet ports.

[Altera_Forum]

Most of the limitation is on the SW side. 

 When talking 1Gbps using GigE, it's the raw bit rate of the Ethernet link. See maximum efficiency in https://en.wikipedia.org/wiki/ethernet_frame. In theory, 970Mbps is possible over GigE. The DMA itself can transfer at 1 Gbps: it uses linked lists of descriptors+buffer and these have to be maintained/monitored by the SW and that'is one of the bottle neck. Another bottle neck is for the processor to read the data / flush the caches, going across the L1 & L2 caches to access the external memory.  This said, I am of the same opinion as flz47655 that you shouldn't have major problems getting 1Gbps using 2 GigE links. You may need to tweak a bit the SW and possibly dedicate one of the 2 cores for that.  Regards

[Altera_Forum]

Okay, thanks for the reply. What kind of SW tweaks are you talking about? Linux Ethernet driver modifications or something else? Currently we're getting only about 200 Mbps Ethernet Performance with one Ethernet port. I guess there's quite lot of work to do if we want to get 1 Gbps with one or two GigE links.

[Altera_Forum]

If you are transferring raw data point to point, there is no need to encapsulate the data with IP/UDP etc, so you could bypass the IP stack. 

That would definitely speed up the transfer rate + reduce the packet overhead Then if you are close to 500 Mbps, tweaking the driver or how you use the driver would be necessary. If you are still far from 500 Mbps, the Linux driver tweaking may be a bit too cumbersome.  The other way is to use a basic bare bone EMAC driver, or write one yourself. It's not that difficult as it mostly manipulating linked lists. If you want to try this path, go to: www.code-time.com and fill the request form for our standalone drivers. They are free and provided under a BSD-2 license, so fully modifiable and usable in commercial product. The EMAC driver handles all HPS EMACs on the Altera chips, is completely standalone and very minimalist. The only thing you'll have to supply is the cache maintenance (invalidation / flushing) if the the data is in cached memory. Properly configured & controlled, you should be able to get much higher throughput than your required 500 Mbps.  Regards