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Altera_Forum
Honored Contributor I
780 Views

SoCKit pin assignment

Hi, 

 

I am new with Arrow SoCKit board. I did Hardware and Software Labs, and now, I want to implement my own system. After configuring system in Qsys, it generates hdl files. The top-level file contains entity with a bunch of ports (hps to memory, emac, ...) for which I have to make pin assignment. This is where the problem rises for me. I do not know how to do that. I did it for simple designs with my Altera DE0 board before, by manually editing locations in Pin Editor, but this seams much more complex. I suppose this is not done manually. I read that this can be done by executing TCL script generated by Qsys, but how TCL script knows where I want to connect my ports ? It must have some external info, in some file or something ... (I am not familiar with scripts). Any help will be very important for me. 

 

Thanks in advance, 

Igor
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2 Replies
Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

 

I did it for simple designs with my Altera DE0 board before 

 

--- Quote End ---  

 

This thread has a project with scripts for the DE0-nano ... 

 

http://www.alteraforum.com/forum/showthread.php?t=45927 

 

For the SoCKit, you should be able to export a Tcl script for an existing project, and then break up that script into the constraints script like I have provided for the DE0-nano. 

 

The "key" to using scripts is that you should always use a top-level entity with all the pin assignments on the physical PCB, and the pin assignments script provide assignments to the ports (pins) on that top-level entity. If a design does not use a particular signal, then any outputs can either be driven to a valid logic level, or tristated. Look at the de0_nano.vhd top-level design for an example. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
43 Views

Thank you Dave. I did it. It works !!!

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