07-28-2017 07:10 AM
Hello all,I am trying to simulation a Qsys system that contains an HPS but I get the following error in Modelsim :
Fatal: (vsim-3362) The type of VHDL port 'clk' is invalid for Verilog connection (2nd connection).# Time: 0 ps Iteration: 0 Instance: /hps_sim_program_top/i_soc_system_tb/soc_system_inst/hps_0/fpga_interfaces/h2f_reset_inst File: ../src/qsys/soc_system/testbench/soc_system_tb/simulation/submodules/altera_avalon_reset_source.vhd Line: 21This error appears when I generate the sources in VHDL and not when they are in Verilog. Is there any tip to know or is this a limitation/bug in Qsys ? All our custom sources are in VHDL so I would feel more comfortable if I was able to work with this language for the testbench also... Thanks for your help Best regards, Romain
07-28-2017 09:29 AM
Without seeing the code, I cant see what the problem is.But I do know most Altera IP is generated in Verilog/SV, with VHDL wrappers (if they even bother to provide one). There could be some error in the code generation somewhere that may need a ticket raising.