Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Soc simulation in VHDL

Honored Contributor II

Hello all, 


I am trying to simulation a Qsys system that contains an HPS but I get the following error in Modelsim :  

Fatal: (vsim-3362) The type of VHDL port 'clk' is invalid for Verilog connection (2nd connection).# Time: 0 ps Iteration: 0 Instance: /hps_sim_program_top/i_soc_system_tb/soc_system_inst/hps_0/fpga_interfaces/h2f_reset_inst File: ../src/qsys/soc_system/testbench/soc_system_tb/simulation/submodules/altera_avalon_reset_source.vhd Line: 21 

This error appears when I generate the sources in VHDL and not when they are in Verilog. Is there any tip to know or is this a limitation/bug in Qsys ? 


All our custom sources are in VHDL so I would feel more comfortable if I was able to work with this language for the testbench also... 


Thanks for your help 

Best regards, 

0 Kudos
2 Replies
Honored Contributor II

Without seeing the code, I cant see what the problem is.  

But I do know most Altera IP is generated in Verilog/SV, with VHDL wrappers (if they even bother to provide one). There could be some error in the code generation somewhere that may need a ticket raising.
Honored Contributor II

Ok thanks, I will check the generated code and open a ticket if needed