Software runs w/o reloading on changed FPGA design

[Altera_Forum]

Help me understand following observation: 

 1. I have created FPGA design with Signal Tap, NIOS II cpu, 4k of internal RAM, EPCS flash.  2. I have created a piece of software linked to be copied into internal RAM  - cpu reset vector points to EPCS flash area so the copier was added to move code to ram  3. I have programmed EPCS flash using NIOS IDE programmer and run my software by cycling power.  4. Software runs great, fast blinking my LEDs as designed... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif   5. I have changed my fpga design, adding a frequency divider in front of cpu-clock... (freq/4)  6. I have run Quartus JTAG programmer to load new design into FPGA  7. After reset, my software just run as usuall, just 4 times slower.  8. I am able to Signal Tap and see effects of the software running (memory fetches, etc)   Why re-loading fpga via JTAG did not reset software/ram area of the fpga device?   After I cycled power LEDs started blinking fast, as in original design written into EPCS (without frequency divider). When I switched back to Quartus and JTAG chain was scanned from Quartus, my Signal Tap did not run requiring fpga re-programming. After re-programing from Quartus via JTAG the software is running 4 times slower again...  What is going on? Is it normal? Anybody can explain what is happening?

[Altera_Forum]

I **think** (I could be wrong) that it is because when it is running fast, it is running out of flash. WHen you download a design, that design starts running (not the one in flash). When you powercycle the board, it starts out of flash again.

[Altera_Forum]

--- Quote Start ---  originally posted by kerri@Jul 12 2004, 12:15 PM i **think** (i could be wrong) that it is because when it is running fast, it is running out of flash. when you download a design, that design starts running (not the one in flash). when you powercycle the board, it starts out of flash again.  --- Quote End ---   I am not sure if you get my question right... I asked:  <div class='quotetop'>QUOTE </div>  --- Quote Start ---  "Why re-loading fpga via JTAG did not reset software/ram area of the fpga device?"[/b]  --- Quote End ---    I am not surprised with the fact that when I am running a design with a frequency divider the code is running slower - it is kind of obvious. I am suprised that changing fpga design did not force on me code recompilation and reloading.

[Altera_Forum]

Another observation today - I went to SOPC Builder to change the timing on my external SRAM memory configured as a User Logic on a Avalon tri-state bus. I have re-generated nios microcontroller in SOPC builder. After this was done, I closed SOPC Builder app and went back to Quartus, opened main schematic page, updated nios symbol, saved the file and re-compiled my project. 

I did NOT program my FPGA but the Signal Tap had "Ready to acquire" status. So I tried to acquire data and everything worked fine, like no of my timing changes took effect (of course, they were not sent to the chip!).  Very strange - Quartus did not recognise the design has changed and the chip should be reprogrammed before a datascope can be acquired.   Is this a bug or a feature? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

[Altera_Forum]

Bug. 

At least if things should have changed it&#39;s a bug. I haven&#39;t worke don Signal Tap for 3-4 years, so it&#39;s hard for me to remember. Plus it&#39;s been re-written.

[Altera_Forum]

--- Quote Start ---  originally posted by pszemol@Jul 9 2004, 04:45 PM why re-loading fpga via jtag did not reset software/ram area of the fpga device?   after i cycled power leds started blinking fast, as in original design written into epcs (without frequency divider). when i switched back to quartus and jtag chain was scanned from quartus, my signal tap did not run requiring fpga re-programming. after re-programing from quartus via jtag the software is running 4 times slower again...  --- Quote End ---   When you reconfigure the FPGA via JTAG, the M4K memories do get re-initialized. However, it sounds like you have setup your Nios II boot address so that it points to the EPCS device. This means that whenever the Nios II processor comes out of reset (such as when the FPGA is reconfigured), it&#39;s going to run the boot copier out of the EPCS device all over again. But since you just reconfigured the FPGA with a Nios II running 1/4 the speed, it&#39;s going to run the software 4 times slower. When you power cycle, the FPGA is automatically configured with the image stored in the EPCS (the Nios II with no clock divider). This processor then boots from the EPCS, runs the boot copier, jumps to RAM, and the LED blinker runs again at full speed.  Hope this helps.  Nate Knight Altera