Hello,is there a way to tell the iniche package which memory region it could use? I have attached a screenshot which shows the memory layout I want to implement and the other screenshot show the memory which I'm talking about. Best regards Martin
Thanks a lot!Can you tell me if these defines are the ones I'm interested in (p. 10 in AN 440)?: # define BB_ALLOC(size) ncpalloc(size) # define BB_FREE(ptr) ncpfree(ptr) # define LB_ALLOC(size) ncpalloc(size) # define LB_FREE(ptr) ncpfree(ptr) On this page it is also mentioned that this RAM should be placed in an uncached region under certain circumstances but I haven't really understood that part. Does the driver handle this for me? I've read in cache and tightly-coupled memorycache and tightly-coupled memory (http://www.altera.com/literature/hb/nios2/n2sw_nii52007.pdf) that one can tell the processor that the memory should be accessed not using the cache by setting the MSB of the address to '1'. This application note is really interesting. In this document it's also mentioned that checksum generation could be greatly improved if using a dedicated hardware resources on the FPGA. Do you know if there is an IP core for the Triple-Speed Ethernet MegaCore core available?
Yes this is the part, and you also need to include those functions (ncpalloc/ncpfree) in your project. IIRC they are in a file called optimisations.c in the example project. Those functions are the ones that will take care of allocating the buffers in the on-chip memory, and will set them as uncached (either by setting the address MSB to 1 or by using the more futureproof alt_remap_uncached() function).I don't think there is a ready made checksum IP available, at least not on the Altera website. You could check Opencores.org, but I don't think it would be very complicated to do it yourself.
This looks just like what I was looking for. Thanks again!As for the IP core: I've never made a custom instruction core and I don't have any time left in this project. But I will keep this in the back of my mind.