Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
748 Views

Spurious end of packet with timing adapter

SOPC system looks like: 

 

NIOS->Onchip FIFO(MM-ST)->Ava ST Timing Adapter-> Ava ST Data format adapter 

-> conduit(to get out of SOPC and into my VHDL). 

 

Packets are supported and the adapters are auto inserted between FIFO and the conduit. 

FIFO is 32 bit and conduit is 64 bit. 

 

Problem is that a spurious endofpacket(eop) occurs between the real startofpacket(sop)  

and the final and real eop that causes the packet to be chopped up. I control the eop with  

writes to the FIFO from NIOS and I know that when I write eop I also write empty as 2 and  

empty is not 2 when the spurious eop occurs but is 2 when the final and real eop occurs. 

 

Using signaltap I managed to see that the FIFO spits out correct eop going into 

the timing adapter but the timing adapter spits out the spurious eop. 

 

Any advise on how to resolve this would be appreciated. 

 

Regards, 

 

Cos
0 Kudos
0 Replies
Reply