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Start and done ports of multicycle custom instruction

Altera_Forum
Honored Contributor II
744 Views

Hi everyone, 

 

I have read through the NIOS II Custom Instruction User Guide and there is one thing I am not really clear about: 

 

For a variable multicycle custom instruction, the ci master asserts start for one cycle, and the done output should notify the processor once the result is valid. However, what I am wondering is, isn't the information contained in start and done highly correlated to the information in clk_en?  

I.e.: Rising edge of clk_en <-> start; falling edge of clk_en <-> done. 

 

Is that right or is there something wrong in my thinking? 

 

And if I am right, so why would you still need extra start and done ports then? 

 

Many thanks. 

 

Jimmy
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Altera_Forum
Honored Contributor II
77 Views

That wouldn't work at all for instructions that take a variable number of cycles. 

 

I'd actually check that 'clk_en' isn't actually used when the processor needs to stall the custom instruction unit because of a pipeline stall somewhere. In which case 'done' would only be actioned when 'clk_en' was valid. 

 

I've only written combinatorial instructions though. 

If something is a 'bit too slow' for a single cycle combinatorial instruction it might be worth using 2 instrcutions and cycling a 32bit intermediate through a cpu register. That would give a 2 cycle instruction with no result delay.
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