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Altera_Forum
Honored Contributor I
835 Views

Starting point for DE1 Board

Hi all, 

Recently i have buy the Altera DE1 Board. 

 

My objectif is to make a projects with Nios II F and all the things with a commented source for everyone want to start a project with DE1 and C code with the Eclipse IDE. 

 

After i want to send it to the wiki and here for exemple. 

 

I have succesfully integrated and be able to command the Switch , Key and all Led with Nios II Eclipse. 

if someone already want the project and source tell me. 

 

But now i want to add the VGA and i request some help. 

 

so just two question please , i know this forum have several VGA question but i just want to make one starting point project for beginner guys ( like me) who want to start a project. 

 

1) Is it Possible to command the VGA directly with the Nios and Eclipse ( by command the Buffer). 

 

2) I have found the Altera Source Code for the CycloneII_2C35 with the VGA. 

i have added in my SOPC the vga controller and the vid_pll for the 40Mhz clock and 800*600 resolution. 

i can sucessfuly compile my project in Quartus II and Eclipse too but when i flash it i have no signal in my VGA monitor even with Run as Hardware. 

 

Here is my project and my source code , can you tell where is the error ? 

http://sega4ever.power-heberg.com/fpga/de1_nios.rar 

 

Thanks a lot !
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15 Replies
Altera_Forum
Honored Contributor I
72 Views

reserved post for description

Altera_Forum
Honored Contributor I
72 Views

I must need to buy The Microtronix Lancelot Card for doing VGA with DE1 and Nios II ?

Altera_Forum
Honored Contributor I
72 Views

In your top level module it doesn't seem that anything is connected to the VGA outputs, therefore there can't be any VGA output.  

 

If you go to system0_inst.v you will see a number of extra ports that you haven't added (B_from_vga_controller etc.) 

 

First add these ports to your instantiation in DE1_NIOS.v and connect them to the VGA outputs (VGA_R, VGA_G, VGA_B, etc.).
Altera_Forum
Honored Contributor I
72 Views

Hi, 

First thanks for your reply ! 

according to the info in system_0_inst.v 

i have write this : 

http://sega4ever.power-heberg.com/fpga/de1%20init.rar 

 

The Quartus II Compilation works but vga seem's not be initialized when i flash the .sof 

 

Can you tell me if everything is ok in my files ? 

 

Thanks !
Altera_Forum
Honored Contributor I
72 Views

You're just creating nets that don't connect anywhere. They're not connected to any pins. 

 

You need to connect them to the VGA ports defined in your top level module. That is, instead of R, connect it to VGA_R, instead of sync_n, connect to VGA_SYNC_N, etc. 

 

If you look at your top level module, you can find in the port declarations all the ports you didn't connect to : 

 

//////////////////////// VGA //////////////////////////// output VGA_HS; // VGA H_SYNC output VGA_VS; // VGA V_SYNC output VGA_R; // VGA Red output VGA_G; // VGA Green output VGA_B; // VGA Blue output VGA_CLK; // VGA Clock output VGA_BLANK; // VGA Blank output VGA_SYNC_N; // VGA Sync output VGA_SYNC_T; // VGA Sync output VGA_M1; // VGA M1 output VGA_M2; // VGA M2
Altera_Forum
Honored Contributor I
72 Views

Ok i think understand my error i don't have write the new pin in the Pin Planner. 

But according to the DE1 docs they don't have this new pin : 

I only found : 

 

VGA_HS,  

VGA_VS,  

VGA_R,  

VGA_G,  

VGA_B,  

 

with are already writed in the PIN PLANNER  

 

Look at my picture please : 

http://sega4ever.power-heberg.com/fpga/vga%20pinout.png 

 

and here is the DE1 pinout docs : 

http://sega4ever.power-heberg.com/fpga/de1_v11a.pdf 

 

i have missed something ?
Altera_Forum
Honored Contributor I
72 Views

No actually you don't understand at all. 

 

Here's what I mean. In the .rar file you've supplied, you did this: 

 

// the VGA Controller .R_from_the_vga_controller(R), .B_from_the_vga_controller(B), .G_from_the_vga_controller(G), what it should be is this: 

 

// the VGA Controller .R_from_the_vga_controller(VGA_R), .B_from_the_vga_controller(VGA_B), .G_from_the_vga_controller(VGA_G), since those are the names of the outputs you have declared. 

 

I suggest you try to understand Verilog. What your problem was, is that the outputs of your top level module VGA_R, VGA_B, VGA_G, VGA_HSYNC_N, etc. are assigned physically to VGA, but nothing in your Verilog actually drives these signals, therefore there can't be any signal.
Altera_Forum
Honored Contributor I
72 Views

Quartus send me this error during the compilation : 

 

Error (10170): Verilog HDL syntax error at DE1_NIOS.v(345) near text "."; expecting ")" 

Error (10112): Ignored design unit "DE1_NIOS" at DE1_NIOS.v(43) due to previous errors 

 

here is my modification 

 

// the VGA Controller .R_from_the_vga_controller(VGA_R), .B_from_the_vga_controller(VGA_B), .G_from_the_vga_controller(VGA_G), .hsync_from_the_vga_controller(VGA_hsync), .vsync_from_the_vga_controller(VGA_vsync),
Altera_Forum
Honored Contributor I
72 Views

1. Those are syntax errors. You might have deleted a ")". 

 

2. Please use the name of the outputs declared in your top module. That means, not "VGA_hsync", but it should be "VGA_HS", because that was how it's declared in the top module. Using "VGA_hsync" just creates a net that doesn't connect anywhere. 

 

3. Remember that in verilog everything is case sensitive. "VGA" is not the same as "vga" or "Vga". 

 

 

I suggest you refer to a Verilog tutorial ASAP.
Altera_Forum
Honored Contributor I
72 Views

Ok i have rewrited the DE1_NIOS.v with your indications. 

Thanks for your patience really :oops:. 

So actually here is the state of my two files : 

http://sega4ever.power-heberg.com/fpga/de1%20init.rar 

 

i think this : 

VGA_M1, // VGA M1 VGA_M2, // VGA M2 VGA_SYNC_N, // VGA SYNC N VGA_SYNC_T, // VGA SYNC T VGA_BLANK, // VGA Blank VGA_CLK, Are part of the Lancelot card so i can't drive it with Nios II eclipse because i don't have the card attached in my FPGA  

I have commented these lines in my DE1_NIOS.v . 

Just need to drive the VGA with Nios II Eclipse ;) 

 

The Quartus II compilation works but nothing seems to be initialized when i launch the vga demo with eclipse.  

 

Can you tell me one more time if my files are correct please ?
Altera_Forum
Honored Contributor I
72 Views

It's still not correct. 

 

Here, replace this section of your code: 

 

system_0 u0 ( // 1) global signals: .clk(CPU_CLK), .reset_n(CPU_RESET), // the_KEY .in_port_to_the_KEY(KEY), // the_LEDG .out_port_from_the_LEDG(LEDG), // the_LEDR .out_port_from_the_LEDR(LEDR), // the_SEG7 .oSEG0_from_the_SEG7(HEX0), .oSEG1_from_the_SEG7(HEX1), .oSEG2_from_the_SEG7(HEX2), .oSEG3_from_the_SEG7(HEX3), // the_Switch .in_port_to_the_Switch(SW), // the_sdram_0 .zs_addr_from_the_sdram_0(DRAM_ADDR), .zs_ba_from_the_sdram_0({DRAM_BA_1,DRAM_BA_0}), .zs_cas_n_from_the_sdram_0(DRAM_CAS_N), .zs_cke_from_the_sdram_0(DRAM_CKE), .zs_cs_n_from_the_sdram_0(DRAM_CS_N), .zs_dq_to_and_from_the_sdram_0(DRAM_DQ), .zs_dqm_from_the_sdram_0({DRAM_UDQM,DRAM_LDQM}), .zs_ras_n_from_the_sdram_0(DRAM_RAS_N), .zs_we_n_from_the_sdram_0(DRAM_WE_N), // the_tri_state_bridge_0_avalon_slave .select_n_to_the_cfi_flash_0(FL_CE_N), .tri_state_bridge_0_address(FL_ADDR), .tri_state_bridge_0_data(FL_DQ), .tri_state_bridge_0_readn(FL_OE_N), .write_n_to_the_cfi_flash_0(FL_WE_N), // the_uart_0 .rxd_to_the_uart_0(UART_RXD), .txd_from_the_uart_0(UART_TXD), // the_sram_0 .SRAM_ADDR_from_the_sram_0(SRAM_ADDR), .SRAM_CE_N_from_the_sram_0(SRAM_CE_N), .SRAM_DQ_to_and_from_the_sram_0(SRAM_DQ), .SRAM_LB_N_from_the_sram_0(SRAM_LB_N), .SRAM_OE_N_from_the_sram_0(SRAM_OE_N), .SRAM_UB_N_from_the_sram_0(SRAM_UB_N), .SRAM_WE_N_from_the_sram_0(SRAM_WE_N), // the VGA Controller .R_from_the_vga_controller(VGA_R), .B_from_the_vga_controller(VGA_B), .G_from_the_vga_controller(VGA_G), .hsync_from_the_vga_controller(VGA_hsync), .vsync_from_the_vga_controller(VGA_vsync), /* Commented becaue don't have the lancelot Card .M1_from_the_vga_controller(VGA_M1), .M2_from_the_vga_controller(VGA_M2), .sync_n_from_the_vga_controller(VGA_sync_n), .sync_t_from_the_vga_controller(VGA_sync_t), .vga_clk_to_the_vga_controller(VGA_vga_clk), .blank_n_from_the_vga_controller(VGA_blank), */ ); 

 

with this: 

 

system_0 u0 ( // 1) global signals: .clk(CPU_CLK), .reset_n(CPU_RESET), // the_KEY .in_port_to_the_KEY(KEY), // the_LEDG .out_port_from_the_LEDG(LEDG), // the_LEDR .out_port_from_the_LEDR(LEDR), // the_SEG7 .oSEG0_from_the_SEG7(HEX0), .oSEG1_from_the_SEG7(HEX1), .oSEG2_from_the_SEG7(HEX2), .oSEG3_from_the_SEG7(HEX3), // the_Switch .in_port_to_the_Switch(SW), // the_sdram_0 .zs_addr_from_the_sdram_0(DRAM_ADDR), .zs_ba_from_the_sdram_0({DRAM_BA_1,DRAM_BA_0}), .zs_cas_n_from_the_sdram_0(DRAM_CAS_N), .zs_cke_from_the_sdram_0(DRAM_CKE), .zs_cs_n_from_the_sdram_0(DRAM_CS_N), .zs_dq_to_and_from_the_sdram_0(DRAM_DQ), .zs_dqm_from_the_sdram_0({DRAM_UDQM,DRAM_LDQM}), .zs_ras_n_from_the_sdram_0(DRAM_RAS_N), .zs_we_n_from_the_sdram_0(DRAM_WE_N), // the_tri_state_bridge_0_avalon_slave .select_n_to_the_cfi_flash_0(FL_CE_N), .tri_state_bridge_0_address(FL_ADDR), .tri_state_bridge_0_data(FL_DQ), .tri_state_bridge_0_readn(FL_OE_N), .write_n_to_the_cfi_flash_0(FL_WE_N), // the_uart_0 .rxd_to_the_uart_0(UART_RXD), .txd_from_the_uart_0(UART_TXD), // the_sram_0 .SRAM_ADDR_from_the_sram_0(SRAM_ADDR), .SRAM_CE_N_from_the_sram_0(SRAM_CE_N), .SRAM_DQ_to_and_from_the_sram_0(SRAM_DQ), .SRAM_LB_N_from_the_sram_0(SRAM_LB_N), .SRAM_OE_N_from_the_sram_0(SRAM_OE_N), .SRAM_UB_N_from_the_sram_0(SRAM_UB_N), .SRAM_WE_N_from_the_sram_0(SRAM_WE_N), // the VGA Controller .R_from_the_vga_controller(VGA_R), .B_from_the_vga_controller(VGA_B), .G_from_the_vga_controller(VGA_G), //HERE IS WHERE YOU WENT WRONG .hsync_from_the_vga_controller(VGA_HS), .vsync_from_the_vga_controller(VGA_VS), .M1_from_the_vga_controller(VGA_M1), .M2_from_the_vga_controller(VGA_M2), .sync_n_from_the_vga_controller(VGA_SYNC_N), .sync_t_from_the_vga_controller(VGA_SYNC_T), .vga_clk_to_the_vga_controller(VGA_VGA_CLK), .blank_n_from_the_vga_controller(VGA_BLANK) ); 

And please uncomment this section: 

 

/*Commented becaue don't have the lancelot Card output VGA_CLK; // VGA Clock output VGA_BLANK; // VGA Blank output VGA_SYNC_N; // VGA Sync output VGA_SYNC_T; // VGA Sync output VGA_M1; // VGA M1 output VGA_M2; // VGA M2VGA needs to have these parameters.
Altera_Forum
Honored Contributor I
72 Views

Ok i have write your modification. 

Thanks you very much ! 

Compilation works and in the pin planner some new nodes appear. 

But nothing more with monitor. 

Here is my actual project including the software part: 

http://sega4ever.power-heberg.com/fpga/de1_nios.rar 

I think he should not miss much thing now :cool:
Altera_Forum
Honored Contributor I
72 Views

I made a typo. Shouldn't be "VGA_VGA_CLK", it should be "VGA_CLK" according to your input and output declarations (which I keep telling you to look at). You can't name the signals anything you want and expect it to work! 

 

Also, you need to connect the net VGA_CLK to a clock. The frequency depends on your resolution. If it's 640x480 vga, use a 25Mhz clock. If 800x600 use 40 MHz. 

 

So what you need to do is the following: 

 

1. Create a PLL from Megawizard (ALTPLL) and create a 40 MHz or 25 Mhz clock. It should take an input clock (inclk0) of 50Mhz and an output clock (c0) of 25 Mhz or 40 Mhz. Name it vga_pll and add it to project. If you don't know how to do this look at the documentation. 

 

2. Add this code to DE1_NIOS.v: 

 

vga_pll pll1 ( .inclk0(CLOCK_50), .c0(VGA_CLK) //25 or 40 Mhz );  

 

Also, please refer to this tutorial: 

 

http://www.asic-world.com/verilog/veritut.html 

 

What I just told you is very basic Verilog.
Altera_Forum
Honored Contributor I
72 Views

Thanks! 

 

I already have a PLL with the "inclk0(CLOCK_50)" 

 

SDRAM_PLL PLL1 (.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK)); So i have made c2 in 40Mhz and writted this: 

 

SDRAM_PLL PLL1 (.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK),.c2(VGA_CLK)); Compilation seems to works but with no change. 

 

did you want my project ?
Altera_Forum
Honored Contributor I
72 Views

HI, 

Did someone could help me please ? 

i have integrated the VGA_Controller in SOPC Builder and wire the pins , but vga seems not be initialized when i flash my .sof.
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