Hi,I have just bought a DE0 Nano development board and am fairly new to this. I wish to store my Nios II program in non-volatile memory such as the EEPROM so that when I power up the board, it can run automatically. I am however able to store my generated bit file from VHDL code in the EEPROM and gets transferred to the FPGA on start-up but how do I also store the NIOS II executable program there so it too can run on start-up? Many thanks for any help in advance.
You store the program in flash, called EPCS. In Qsys you can add an EPCS controller. After you flash sof and elf file you can then boot your stored program from start-up.
The best way that I have found so far, is the following:1. When you have built your code, right click on the BSP project in the project explorer panel and select 'make targets'. Double click mem_init_generate. 2. In your quartus project with all your logic and CPU stuff in, you now must add the QIP file, somewhere (i cant remember exactly where), in your project folders for the CPU stuff, will be a folder named software. In here will be the APP and BSP folders and in one of these you will find the QIP file which may be named mem_init.qip or it may have your_project_name.qip. So in Quartus select Project and Add/Removes FIles in project, click the '...' button and point to your qip file you just generated and click add. 3. This step may not be neccessary but I always do it to be safe, rebuild your quartus project now this file is added. 4. You now need to generate a .jic file. CLick file menu and choose Convert Programming File. Set programming file type to .JIC (assuming use of JTAG), and select config device you are using and the mode. I use EPCS16 and active serial mode. 5. give it a file name and location using the '...' button. 6. In the window at the bottom, click flash loader, and select your FPGA after pressing the 'add device button'. THe FPGA will be used to load it all into the EPCS from JTAG. 7. click SOF data and select your quartus project SOF from the outputs folder of your project, by pressing the 'add file' button. 8. Hit generate. This will generate the jic file in the outputs folder. 9. Now program the FPGA with the .jic file. 10. On reset/power up you code should run. I apologise if I missed some steps or i misnamed some files/folders, its been a while. Hope this helps. D BTW I should have added that you dont need to add EPCS controller in QSYS to do this.