Storing states between 2 custom instructions with Nios II processor

[Altera_Forum]

I need to save states of a finite state machine between two custom instructions. Is there any way of doing it?Thanks for any help you could provide.

[Altera_Forum]

Provided you aren't using a combinatorial instruction you can just keep the values in any latch/memory etc. Just make sure the processing is correctly gated by the start (and generated done) signals. 

Combinatorial custom instructions don't have an enable/select signal at all, the output value is just fed into a big mux and the result selected (for writeback to rC) if the instruction is actually a custom opcode with the required sub-code. So you can't save any state (except by passing it back in rC).

[Altera_Forum]

Yeah. I'm using multi cycle Custom Instruction (CI). The problem is I'm giving my input part by part using the same in a loop. Therefore I have a problem of resetting all the signals at the beginning of each CI. So I have to keep FSM state values in memory after calling one instruction. Can I do that in multi cycle custom instruction method? 

 Thanks for replying.

[Altera_Forum]

One thing to remember is that the custom instruction inputs are (almost) all of the 32 bits of the instruction word, and the two registers values corresponding to the rA and rB fields. What you actually use them for is up to you. 

I've not actually determined whether the readra and readrb make any difference, my suspicion is that the logic to suppress the pipeline stall (when they are not asserted) would be too complex. For all other instructions (except call/jmp) only the two lsb bits of the opcode have to be inspected (NFI why it isn't just 1 bit!).

[Altera_Forum]

Thanks. I'm still not understanding the process meant by suppressing pipeline stall and it seems here you describe internal register file mode. If you have an example for that could you please send me.