Dear collegue engineers, I have been working with the NIOS II kit for a few weeks now and I have pretty much all of my interface/peripheral chips linked together. The only thing that I am still struggling with is opening a channel between my user logic module (running at 4MByte / second data rate) and my SDRAM (running at 20MHz). I use the dataavailable_n line to negotiate timing with the avalon bus, but that is not working in all cases (instantiated with SOPC-builder/Quartus II 4.2). The bus seems to stall, even when the dataavailable_n line (DAn-line) is asserted. If I tie the DAn low continuously, it runs but it is - of course - completely out of sync with me data channel. Anybody any experience with DMA handshake? I avoid using the HAL completely, because that is locking up the system completely. I use register addressing (as found in the altera_avalon_dma_regs.h, and I enabled only 16-bit (HW) transfer. I am fighting this bug for a few days now... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif
Arjan,Not to put a damper on things, but we spent months trying to get Streaming DMA to work flawlessly. We gave up and inserted a fifo that interrupts the Nios and then dma the fifo contents into sdram. Mike D. has a peripheral that may help with this approach in the Post your IP section. We just used a standard LPM_FIFO and and IUL though. Ken
Arjan,Streaming can certainly be tricky. Given your brief description, I wonder if your dataavailable_n signal could be misbehaving. I believe if a streaming signal changes midway through a transaction, the arbitration logic might become confused. Can you make sure your dataavailable_n goes to inactive level only on the cycle after data is delivered, or when the slave interface is idle?
Thanks for the input Ken. I had no idea it was that tricky, but it seems to be working now though. After more digging I found out that the dataavailable line is also de-activating the CSn signal. That's not good, because I am starting my peripheral with a few write operation, and keep the DA line inactive until the data stream starts. Since those write operations are not happening, the peripheral doesn't start and the DMA is not initiated at all. So after changing that, it seems to run stable; but now the NIOS is slowing down by about 30%. Should I make the fifo in the DMA controller a bit deeper to minimize interrupt overhead?