I am using EMAC0 in a Cyclone V HPS system. On a development board with a similar device (not exactly the same package, but a dual-core ARM Cyclone V part nonetheless) I can set up the MAC/PHY (same PHY, too, on both boards) and send/receive packets just fine.
But on this new board, I can't get anything through. On RX (receiving packets from the network) I can send an ARP packet to my system and see it perfectly represented on the RGMII buss between the PHY and MAC/Cyclone V. The timing looks good (clock centered in the data) and the bytes on the bus are exactly what I expect from preamble through FCS. But the MAC will either ignore this or report a CRC/Framing error (I've tried both 100 and 1000 Mb/s modes... same results).
Is there any debugging method to see what the MAC is seeing besides looking at the counters? I've tried setting the DT and FEF bits int he MAC DMA OPMODE register to try and get it to give me frames with bad CRCs so I can see what it sees, but this never gives me anything, either (except an occasional frame with all zeros in the data).
What am I missing?
I guess I don't fully understand this. I am looking at the MAC registers in DS-5, but that's not a low enough view. I send seven ARP packets, and see one or two packets received, both with one or more errors (CRC/Alignment/etc.). That's not enough information, I don't think. My logic analyzer and scope show a very nice looking ARP packet going to the FPGA, so why such errors at the MAC?
Are you suggesting there is a way to get internal information from the MAC with Signal Tap? Is this documented? I've never seen that.
The logic analyzer will give you information until FPGA level. Inside FPGA we need to know what is going on. So, You can map HPS signals to FPGA and then you can use signaltap to trace signals.
This tutorial will help you: