System ID on FPGA is not match

[Altera_Forum]

Hi, 

 I design Compact Flash Controller (in True IDE mode) using Nios 2 core (version 1.1) and software to test. I don't download the software by Nios II IDE tool. The tool informed the following information:  "Reading System ID at address 0x021208D8: does not match  ID value does not match: read 0xFFFFFFFF; expected 0xE62A3C72  Timestamp value does not match: image on board is older than expected  Read timestamp 6:59:59 1970/01/01; expected 9:47:36 2006/01/20 The software you are downloading may not run on the system which is currently configured into the device "  On the other, when I compile the design, Quartus software informed that  - Full compilation has NO error  And when I call Programmer from Quartus II (version 4.2), it inform the following information:  "File standard_time_limited.sof contains one or more time-limited megafunctions that support the OpenCore Plus feature that will not work after the hardware evalution time expires."  I'm using Nios Delelopment Kit Stratix Edition and I had a licence from Altera.  Any ideas what I can do to solve this problem? I'm sorry. My English is not very good.  Thanks to everyone who can help me solving this problem.  Bye Hai

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  "Reading System ID at address 0x021208D8: does not match     ID value does not match: read 0xFFFFFFFF; expected 0xE62A3C72     Timestamp value does not match: image on board is older than expected     Read timestamp  6:59:59 1970/01/01; expected  9:47:36 2006/01/20 The software you are downloading may not run on the system which is currently configured into the device "[/b]  --- Quote End ---    when you write a program for nios you are writen it for a specific target board. this error means that the fpga is configure to a different target board then the one your program was written for. you should program the fpga again. goto nios II ide ->tools-> quartus II progrmer and download the correct image to the fpga     <div class='quotetop'>QUOTE </div>  --- Quote Start ---  And when I call Programmer from Quartus II (version 4.2), it inform the following information:  "File standard_time_limited.sof contains one or more time-limited megafunctions that support the OpenCore Plus feature that will not work after the hardware  evalution time expires."[/b]  --- Quote End ---    this means that you have generated your system (with SOPC builder) without a valid license . if you don&#39;t have a valide license you won&#39;t be able to make the system run. if you don&#39;t have a valide license you can only use the example desgin altera supplied

[Altera_Forum]

I had the same problem  

 I have permanent license for nios2 and NIOS2 1c20 development kit  I download and install NIOS5.1 release from ALTERA and  Quatus 5.1 Build 176 10/26/2005 SJ WEB Edition   About NIOS5.1  I download this file  ftp://ftp.altera.com/outgoing/release/nios_ii_51_release.zip (ftp://ftp.altera.com/outgoing/release/nios_ii_51_release.zip)  after install  C:\altera\kits\nios2_51\version.txt tell me this Kit: Nios II, Version: 5.1, Build: 73b    I try to work with new NIOS5.1 2 times   And I can describe in details all my steps   1. I open full featured example in Quatrus and open NIOS block in SOPC builder  2. I re-generate system without any changes  3. After this i press "Run NIOSII IDE" button  4. I close SOPC Builder  5. recompile project in Quatrus  6. go to NIOS IDE  7. and run File->new->C/C++ Application  8. Select Hello Word (in project templates) This SOPC Builder system was assigned C:\altera\kits501\nios2\examples\verilog\niosII_cyclone_1c20\full_featured\full_1c20.ptf 9. Pres NEXT button  10. Select Create a new system Library  11. Press Finish button  12. and i got Hello_word_0 project and system library  13 I make right-click mouse button on Hello_word_0 and select build project - build was success 14 I take my 1c20 board -connect USB blaster to J24 and connect power jack  15. after this select Tools->FlashProgrammer  16. I create new  17. click to a Programm FPGA configuration data into hardware-image of flash memory 18. press programm flash  and got next  # ! /bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.#   cd C:/altera/kits501/nios2/examples/verilog/niosII_cyclone_1c20/full_featured/so ftware/hello_world_0/Debug # Creating .flash file for the FPGA configuration $SOPC_KIT_NIOS2/bin/sof2flash --offset=0x600000 --input=C:/altera/kits501/nios2/ examples/verilog/niosII_cyclone_1c20/full_featured/full_featured.sof --output=fu ll_featured.flash Info: ******************************************************************* Info: Running Quartus II Convert_programming_file Info: Command: quartus_cpf --no_banner --convert C:/altera/kits501/nios2/example s/verilog/niosII_cyclone_1c20/full_featured/full_featured.sof full_featured.rbf Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings  Info: Processing ended: Wed Feb 01 11:35:49 2006  Info: Elapsed time: 00:00:01 # Programming flash with the FPGA configuration $SOPC_KIT_NIOS2/bin/nios2-flash-programmer --cable=&#39;USB-Blaster [USB-0]&#39; --sidp= 0x021208D8 --id=1517107964 --timestamp=1138697041 --base=0x00000000 full_feature d.flash Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Reading System ID at address 0x021208D8: FAIL  ID value does not match: read 0xFFFFFFFF; expected 0x5A6D3AFC  Timestamp value does not match: image on board is older than expected  Read timestamp 1:59:59 1970/01/01; expected 10:44:01 2006/01/31 Leaving target processor paused # Creating .flash file for the project $SOPC_KIT_NIOS2/bin/elf2flash --base=0x00000000 --end=0x7fffff --reset=0x0 --inp ut=hello_world_0.elf --output=ext_flash.flash --boot=$SOPC_KIT_NIOS2/components/ altera_nios2/boot_loader_cfi.srec # Programming flash with the project $SOPC_KIT_NIOS2/bin/nios2-flash-programmer --cable=&#39;USB-Blaster [USB-0]&#39; --sidp= 0x021208D8 --id=1517107964 --timestamp=1138697041 --base=0x00000000 ext_flash.fl ash Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Reading System ID at address 0x021208D8: FAIL  ID value does not match: read 0xFFFFFFFF; expected 0x5A6D3AFC  Timestamp value does not match: image on board is older than expected  Read timestamp 1:59:59 1970/01/01; expected 10:44:01 2006/01/31 Leaving target processor paused ????????????????????????????????????????????????????????????????????????????? WHAT WRONG ?  currently i use nios2 Kit: Altera Nios II Development Kit, Version: 1.0 Service Pack 1, Build: 393b, Patch i think it most stable version  and way described above all times was work fine  what i miss ?

[Altera_Forum]

AlexS, 

 The error in your flow is steps 15-18  15. after this select Tools->FlashProgrammer  16. I create new  17. click to a Programm FPGA configuration data into hardware-image of flash memory 18. press programm flash  You don&#39;t use the NIOS II IDE Flash programmer until you have configured the FPGA first. Once you have a .sof programming file in your Quartus II project, you have to start the Quartus II programmer: Tools --> Programmer From this programmer you need to configure the FPGA with the .sof file (Sram Object File) - This has the FPGA design with the NIOS processor - without that there is no "processor" for the IDE or Flash programmer to run on. That is why your system ID is flagged as 0xFFFFFFFF (The FPGA is not configured!).  I strongly recommend to check out the NIOS II getting started tutorial as it shows you the complete steps to downloading a design to an FPGA and using the NIOS II IDE to download a program. The FlashProgrammer is used later when you are ready to commite your design to "stand alone" without the IDE to debug and run the programs.   NIOS II getting started tutorial: http://www.altera.com/literature/ug/ug_nio...ing_started.pdf (http://www.altera.com/literature/ug/ug_nios2_getting_started.pdf) (This has all the steps to get an example design loaded on a dev board)  Flash programer Users Guide: http://www.altera.com/literature/ug/ug_nio..._programmer.pdf (http://www.altera.com/literature/ug/ug_nios2_flash_programmer.pdf) (Check out appendix D on troubleshooting flash programming when you are ready to do flash programming. It cites your problem in the troubleshooting section and how to solve it)  Regards, -ATJ

[Altera_Forum]

Dear Altera developers !  

 I understand that in this case in system must be  JTAG uart and  CPU with debug and sysid   http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/mad.gif   But maybe is it possible somehow to make system where  not present JTAG uart , CPU without debug, and no sysid ?  And where for code downloading used custom board like in previous version  Version: 1.0 Service Pack 1, Build: 393b  I braked down about new nios2 software download system http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif  because i make 2 boards based on nios2 (both under serial production) and now i don&#39;t have any poblem and quastion to hardware - it work good   From other side we want to solve software bags which corrected in new vesrion of nios5.1 - we have very big soft projects   But how i understand it is not possible !!!!!!!!!!!!!!! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/mad.gif  I can&#39;t implement hardware without JTAG debug and sysid because i don&#39;t have free logic elements for it http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif  My project are developed on NIOS2 - and copmatiblity are lost !!!!!!!!!!!!!!!!!!!!!!  Need only old flash pogrammer !!!!!!! HELP please !  if it possible

[Altera_Forum]

--- Quote Start ---  originally posted by alexs@Feb 2 2006, 04:06 AM dear altera developers !   i understand that in this case in system must be  jtag uart and  cpu with debug and sysid   http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/mad.gif   but maybe is it possible somehow to make system where  not present jtag uart , cpu without debug, and no sysid ?  and where for code downloading used custom board like in previous version  version: 1.0 service pack 1, build: 393b  i braked down about new nios2 software download system http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/sad.gif  because i make 2 boards based on nios2 (both under serial production) and now i don&#39;t have any poblem and quastion to hardware - it work good   from other side we want to solve software bags which corrected in new vesrion of nios5.1  - we have very big soft projects   but how i understand it is not possible !!!!!!!!!!!!!!! http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/mad.gif  i can&#39;t implement hardware without jtag debug and sysid because i don&#39;t have free logic elements for it http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/sad.gif  my project are developed on nios2  - and copmatiblity are lost !!!!!!!!!!!!!!!!!!!!!!  need only old flash pogrammer !!!!!!! help please !  if it possible <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12506)  --- quote end ---    --- Quote End ---    Hi AlexS,  You don&#39;t need the JTAG UART or sysid to use the 5.1 flash programmer. The Flash Programmer Users Guide lists the minimum system requirements need to have your own design program the flash in Table 1-1. A minimum system should have a Flash memory interface(CFI), a tri-state bridge and a Nios processor with a minimum debug level of 1. You are ready have two of the three elements.  I understand that your design does not have the room for the minimum Nios II debug core addition of a few hundred LEs. But there is a solution, since FPGA are re-configurable you can always create a copy of your design that has most peripherals removed except for the minimum system requirments for flash programming (and you keep the same pin out).  Once you create a "new" copy of your "flash program only" design with the nios ii debug level set to 1 , you can compile this in Quartus and load this "flash program only" version of your design before you program the flash.  The only difference in the steps you have to follow after you configure the FPGA, is that you have to use the Flash programmer commandline mode to flash program the chip (the IDE flashprogrammer always checks for a valid sysID (if available) and system timestamp based on what I see in the log outputs). Using the commandline mode you can skip the -sidp (system ID peripheral check) and -timestamp (timestamp check of system) -- see below switch choices highlighted in green.   This should allow you to program your Flash chip and then you can configure the FPGA with your original design.  I hope this helps.  Regards, -ATJ  BTW: I think one of the useful features of the new 5.1 flash programmer is that (if you have the room on your FPGA chip) this is a simple way to have your Nios II design have a built in Flash program upgrade path when your design is out in the field.   Flash Programmer options:  C:\>nios2-flash-programmer -h usage: nios2-flash-programmer [-h/--help] [-c/--cable <cable name>]  [-d/--device <device index>] [-i/--instance <instance>]  [-s/--sidp <address>] [-I/--id <id>] [-t/--timestamp <timestamp>]  -b/--base <address> [-e/--epcs]  <action> [-g/--go]  actions can be either:  [--erase-all | --erase <bytes>] [--no-keep-nearby] [--verify] <file>*  --read <filename> [--read-bytes <start>+<size>]   -h/--help Print this message  -Q/--quiet Don&#39;t print anything if everything works  --debug Print debug information   -c/--cable <cable name> Specifies which JTAG cable to use (not needed if  you only have one cable)  -d/--device <device index> Specifies in which device you want to look for the  Nios II debug core (1 = device nearest TDI etc.)  -i/--instance <instance> Specifies the INSTANCE value of the debug core  (not needed if there is exactly one on the chain)   -s/--sidp <address> Base-address of System ID peripheral on target  -I/--id <system-id-value> Unique ID code for target system  -t/--timestamp <time-stamp> Timestamp for target-system (when last generated)  --accept-bad-sysid Continue even if the system ID comparison fails  -b/--base <address> Base address of FLASH/EPCS to operate on  -e/--epcs This operation is on an EPCS flash  -E/--erase <start>+<size> Erase a range of bytes in the flash, or the entire  --erase-all flash before/instead of programming it.  -P/--program Program flash from the input files (the default)  --no-keep-nearby Don&#39;t preserve bytes which need to be erased but  which aren&#39;t specified in the input file  -Y/--verify Verify that contents of flash match input files  <filename>* The names of the file(s) to program or verify   -R/--read <file> Read flash contents into file  -B/--read-bytes <start>+<size> Specify which bytes to read   -g/--go Run processor from reset vector after program.  Input files should be in Motorola S-Record format. Addresses within the files are interpreted as offsets from the base address of the flash. Output files written by the tool are in the same format.  The flash programmer supports all CFI flashes which use the AMD programming algorithm (CFI algorithm 2) or the Intel algorithm (1 or 3).