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TSE_Driver Architecture

Altera_Forum
Honored Contributor II
888 Views

Dear Friends, 

 

In TSE Software Driver Architecture (ug_Ethernet), there is a Memory Block at the bottom of page 141 ( ug_Ethernet page 141),  

 

Is this is External memory, or Packet memory or some thing else ..? 

 

regards 

 

kaushal
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3 Replies
Altera_Forum
Honored Contributor II
143 Views

This memory block is not part of TSE itself. It is the memory device available in your system: sdram, sram or onchip memory.

Altera_Forum
Honored Contributor II
143 Views

 

--- Quote Start ---  

This memory block is not part of TSE itself. It is the memory device available in your system: sdram, sram or onchip memory. 

--- Quote End ---  

 

 

Thanking you for your reply. 

 

It mean this is external to TSE ,  

 

Is packet loss accure if Processor NIOS-II/f received high speed packets?. or in other way how do i increase the processor speed?. or NIOS-II/f had sufficient speed to handle all incoming packets? 

 

NIOS-II/f having system clock is 125Mhz 

 

regards 

 

kaushal
Altera_Forum
Honored Contributor II
143 Views

Besides processor frequency, there are a number of factors affecting maximum speed achieved with data transfer. For example: 

- system architecture 

- network transport protocol  

- dma and cache 

- Nios operating system and number of other tasks running  

You may refer to AN440 for a comprehensive description of methods for improving performance of ethernet applicaitons.
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