I have a working design using the TSE core that is implemented in an Arria Gx II speed grade -5 which we implemented into Quartus 11.1 SOPC system. I have ported the design into a Cyclone V E speed grade -8 (5CEFA7U19C8ES) using Quartus 12.1SP1 SOPC system which is not working. In this new design, the gate array is alive and we are able to run the firmware (tested via LED test points) and we are receiving Tx_CLK (25 Mhz) successfully however when I tried to send constant packets of data there are no messages sent out. I checked the m_tx_en_from_the_triple_speed_ethernet and never becomes active. I copied the exact same SDC file from the original design. I also downloaded the dp7 patch that was meant to fix timing issues. Does anyone have any ideas ?
How is your system designed? Are you using a CPU and software, or are you sending your packets directly to the core? How is it initialized? Do you see any activity on the TSE's tx avalon stream input?
I am using a NIOS connected to an on-chip Memory. From there I have connected a Scatter Gather DMA Controller(Transfer Mode:Memory-to-stream). The SG-DMA is then connected to the TSE. This configuration we have duplicated for both the Rx and the Tx.We send the packets to the core via this SG-DMA We have successfully initialized the TSE core registers We have not checked the Rx yet we are focusing first on the Tx
You were lucky then, it is rare that an Ethernet design works straight out of the box ;)Have you ever used Signaltap? With the node finder you can navigate into the SOPC system and find the avalon stream signals. The most important ones are ready, available, start/end of packet and data.
Thanks for your help, in the end the firmware guy found that he had put the wrong header file. The system now transmits. We haven't checked Rx but it is a carbon copy so it should be relatively straight forward.