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Valued Contributor III
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Text file to Flash to VHDL

Hello, 

 

I am trying to access the contents of a text file (full of binary data) via an array in VHDL on my Cyclone II device. I would like to output one bit per clock cycle to one of my FPGA pins, and I don't want to hard-code this into Quartus because the file is very large. 

 

My plan was to store the file in the Flash memory using Nios Flash Programmer (right after my .sof and .elf file). If I understand all the contents of the Flash memory get loaded into SRAM upon powerup. Could I then read my file contents from SRAM? How quickly could I access the bits (i.e. what is the fastest the clock reading the bits can run at)? And how can I access this from my VHDL files? I am pretty new to this and I couldn't find a tutorial or example on such a topic. Any help would be greatly appreciated... 

 

The SRAM device is ISSI IS42S16800A-7T and the Flash memory is EPCS16SI8N. 

 

Thank you!
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Valued Contributor III
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--- Quote Start ---  

If I understand all the contents of the Flash memory get loaded into SRAM upon powerup. Could I then read my file contents from SRAM?  

--- Quote End ---  

 

That's not correct. Not all the content of flash gets loaded into sram, but only what is needed or, more exactly, what is specified in the bootloader. 

If the text file is included in the Nios application (e.g. in the form of a static const char array, or any other read only data), indeed it will be loaded into sram upon boot and you'll have it available in your code, like a common variable.  

Otherwise, if the file is simply stored in the flash after fpga configuration and elf file, you need to read it directly from the flash device; but this is quite easy with the HAL driver functions. 

 

I don't understand what you mean when you say you want the file to be accessed from vhdl files.
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Valued Contributor III
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What sort of output bit rate are you after?Are you generating the clock edges as well as the data? 

More particularly can you stop the clock if there is no data? 

 

I don't how fast the EPCS memory reads actually are (is it some kind of serial protocol??), but, unless you need a very high rate I don't necessarily see the reason to copy the data to SRAM. 

 

I think someone has done an avalon slave that will (slowly) directly read EPCS memory (some references to execution Nios code directly from EPCS), so maybe you could 'just' dma onto a parallel->serial converter.
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Valued Contributor III
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--- Quote Start ---  

That's not correct. Not all the content of flash gets loaded into sram, but only what is needed or, more exactly, what is specified in the bootloader. 

--- Quote End ---  

 

 

Ah ok good to know, thanks. 

 

 

--- Quote Start ---  

I don't understand what you mean when you say you want the file to be accessed from vhdl files. 

--- Quote End ---  

 

 

 

--- Quote Start ---  

What sort of output bit rate are you after?Are you generating the clock edges as well as the data? 

More particularly can you stop the clock if there is no data? 

 

I don't how fast the EPCS memory reads actually are (is it some kind of serial protocol??), but, unless you need a very high rate I don't necessarily see the reason to copy the data to SRAM. 

 

I think someone has done an avalon slave that will (slowly) directly read EPCS memory (some references to execution Nios code directly from EPCS), so maybe you could 'just' dma onto a parallel->serial converter. 

--- Quote End ---  

 

 

Ideally I would like to achieve 400 Mbps. I realize that might be unattainable or not meet timing constraints. Right now I have a 400 MHz clock coming out of a PLL and would like to output 1 bit per clock cycle (I've looked into DDR at 200 MHz but it looks like that isn't possible with VHDL/Veriliog/AHDL). I'm not sure what you mean by stopping the clock if there's no data? I was hoping to have an array and on each pos clock cycle, I would increment and output an index from the array. I'm just not sure how to get the data from my text file into an array I can access with VHDL/Verilog/AHDL.
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Valued Contributor III
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--- Quote Start ---  

 

Ideally I would like to achieve 400 Mbps. I realize that might be unattainable or not meet timing constraints. Right now I have a 400 MHz clock coming out of a PLL and would like to output 1 bit per clock cycle (I've looked into DDR at 200 MHz but it looks like that isn't possible with VHDL/Veriliog/AHDL). I'm not sure what you mean by stopping the clock if there's no data? I was hoping to have an array and on each pos clock cycle, I would increment and output an index from the array. I'm just not sure how to get the data from my text file into an array I can access with VHDL/Verilog/AHDL. 

--- Quote End ---  

You need to re-phrase (or re-think) your description. What you really want is (please correct what I have stated incorrectly); 

 

1) To generate a 400Mbps signal on an I/O pin 

 

2) The data for that signal should come from an external SRAM 

 

3) How do I load the data into SRAM? 

 

Here's a few questions/answers: 

 

1) For 400Mbps, you could use a DDR I/O pin with a 200MHz clock to the DDR I/O registers. I believe the fastest data rate for LVCMOS is around 167MHz with most devices. Your I/O options are then LVDS or one of the DDR DRAM I/O standards (SSTL, HSTL, and other funny combinations of letters). So what is it you are trying to communicate with? What output voltage swing is acceptable? 

 

2) If the 400Mbps data is being generated using an LVDS pin, and the LVDS SERDES inside that pin is being fed at 8-bits per parallel clock, then the data rate to the SERDES is 400Mbps/8 = 50MB/s. 

 

If your SRAM is 16-bits wide, then you need the SRAM reads to occur at a rate of 25MHz, i.e., every 40ns. This is within the capabilities of SRAM. 

 

The IS42S16800A-7T is sdram not SRAM 

 

http://www.issi.com/pdf/42s16800a.pdf 

 

For that, you would need to check that burst data can be sustained to have an access time that on average is better than 40ns, eg., at 100MHz clock rate, you receive a burst of 4 words, and then no data for the next 12 clocks, i.e., your sustained rate is 4/16 * 100MHz = 25MHz. For SDRAM, you would transfer the burst to a FIFO, and the LVDS SERDES would drain the FIFO. 

 

3) You can write to the SDRAM from your host computer. For example, if you have an Avalon-MM slave SDRAM controller, a NIOS II processor, and ethernet, you can use that to write data to SDRAM. You can also use the USB interface with a JTAG-UART to the NIOS II processor, or the JTAG-to-Avalon-MM master. You could transfer the data from SDRAM to the 400Mbps pin using a DMA master, or write your own Avalon-MM master to 'read' from the SDRAM and internally write to the FIFO, and your 400Mbps pin togging logic would read from the FIFO. 

 

For transceiver testing I use an Avalon bus setup with pattern RAM, capture RAM, control registers, and a JTAG-to-Avalon-MM bridge. I can generate patterns across multiple 8Gbps transceiver links and capture the results to RAM, and check the results match what I expect. For these tests I use the FPGA on-chip RAM. For long patterns I use PRBS generator/checkers (they only require a few logic cells). 

 

Cheers, 

Dave
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Valued Contributor III
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Thank you for the informative reply Dave. 

 

I did mean SDRAM, not SRAM, it was a typo so my mistake! I would like to use my USB Blaster cable to load the file into the memory. Currently the file is in a normal text file with 1s and 0s, and I am guessing this is incorrect and needs to be changed to something else.  

 

I tried opening the nios2-terminal (I have no experience using this) but it told me there are no JTAG UARTs available which match the --device and --instance options. Perhaps the JTAG-to-Avalon-MM option would be easier. I am afraid I have little experience interacting with any of the Nios components. (I do have SDRAM Avalon MM slave and EPCS_Controller Avalon MM slave already incorporated in the Nios CPU however).  

 

If I understand one way to do implement this: 

1) Format text file  

2) Load into SDRAM using USB Blaster via JTAG 

3) Load data from SDRAM into FIFO 

4) Connect pin to read from FIFO at 400Mbps 

 

Any help or advice would be greatly appreciated. I am scouring tutorials, examples, and forum posts to figure these steps out, but I am having difficulties.  

 

Thank you
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Valued Contributor III
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--- Quote Start ---  

 

I did mean SDRAM, not SRAM, it was a typo so my mistake! 

 

--- Quote End ---  

No problem. The sustained performance of the SDRAM needs to meet your I/O requirement. 

 

 

--- Quote Start ---  

 

I would like to use my USB Blaster cable to load the file into the memory. Currently the file is in a normal text file with 1s and 0s, and I am guessing this is incorrect and needs to be changed to something else.  

 

--- Quote End ---  

The Avalon-MM bridge Tcl commands like master_write_32 take 32-bit Tcl variables. I tend to use hexadecimal values in files, read them in Tcl, and write them using the Tcl commands. 

 

 

--- Quote Start ---  

 

I tried opening the nios2-terminal (I have no experience using this) but it told me there are no JTAG UARTs available which match the --device and --instance options. 

 

--- Quote End ---  

If you wanted to go this route, then you also need to write the software on the NIOS processor, and simulate the NIOS system. 

 

 

--- Quote Start ---  

 

Perhaps the JTAG-to-Avalon-MM option would be easier. I am afraid I have little experience interacting with any of the Nios components. (I do have SDRAM Avalon MM slave and EPCS_Controller Avalon MM slave already incorporated in the Nios CPU however).  

 

--- Quote End ---  

I'd recommend using the JTAG-to-Avalon-MM route. 

 

 

--- Quote Start ---  

 

If I understand one way to do implement this: 

1) Format text file  

2) Load into SDRAM using USB Blaster via JTAG 

3) Load data from SDRAM into FIFO 

4) Connect pin to read from FIFO at 400Mbps 

 

--- Quote End ---  

The text file can be whatever format you like. You can read the file using Tcl, and then reformat the data there. Then you would write to SDRAM using the JTAG-to-Avalon-MM commands. 

 

 

--- Quote Start ---  

 

Any help or advice would be greatly appreciated. I am scouring tutorials, examples, and forum posts to figure these steps out, but I am having difficulties.  

 

--- Quote End ---  

There is a webinar on how to use the components. Its not too bad. 

 

Let me know if you get stuck and I can probably put together an example pretty easily. What board are you using? 

 

Cheers, 

Dave
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Valued Contributor III
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Thanks for the reply. 

 

I am using a custom board with a Cyclone II EP2C20Q240.  

 

An example would be great, or if that's too much trouble a set of instructions would suffice as well. I haven't been able to find the webinar you mentioned.  

 

How do I access/incorporate the Avalon-MM commands (I'm not sure what Tcl is)? This may sound like a silly question, but would this be from Quartus or the Nios IDE? I tried browsing through the available files generated by SOPC Builder but couldn't find any.  

 

Most of the resources online consisted of PDFs with high level design explanations. Perhaps I'm not utilizing the altera website to its fullest potential and the information is readily available. I am a novice so excuse my ineptitude.
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Valued Contributor III
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--- Quote Start ---  

 

An example would be great, or if that's too much trouble a set of instructions would suffice as well. 

 

--- Quote End ---  

 

 

Ok. I have a tutorial that I've just about finished. I'll post it next week. 

 

 

--- Quote Start ---  

 

I haven't been able to find the webinar you mentioned.  

 

--- Quote End ---  

 

 

Look for the SystemConsole webinar. 

 

 

--- Quote Start ---  

 

How do I access/incorporate the Avalon-MM commands (I'm not sure what Tcl is)? 

 

--- Quote End ---  

 

Tcl is a scripting language = Tool Command Language. 

 

Quartus has a built in Tcl interpreter, as does Modelsim, and lots of the other EDA tools. 

 

 

--- Quote Start ---  

 

This may sound like a silly question, but would this be from Quartus or the Nios IDE? I tried browsing through the available files generated by SOPC Builder but couldn't find any.  

 

--- Quote End ---  

 

 

SystemConsole is a Tcl GUI, you would use that for the Avalon-MM master commands. 

 

 

--- Quote Start ---  

 

Most of the resources online consisted of PDFs with high level design explanations. Perhaps I'm not utilizing the altera website to its fullest potential and the information is readily available. I am a novice so excuse my ineptitude. 

--- Quote End ---  

 

 

There's definitely a lot of documentation; some good, some bad. You just have to grind through it and find the good stuff :) 

 

Cheers, 

Dave
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Valued Contributor III
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I took a short hiatus on this project but I am resuming it again this week. I found various webinars on Tcl and scripting and I've gone through them.  

 

One thing that is still unclear to me: Tcl seems to give me the tools to fill the on board memory with my data, but how do I set up the FIFO to read in at the correct rate and out to the pin? 

 

Happy holidays
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Valued Contributor III
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--- Quote Start ---  

I took a short hiatus on this project but I am resuming it again this week. I found various webinars on Tcl and scripting and I've gone through them.  

 

One thing that is still unclear to me: Tcl seems to give me the tools to fill the on board memory with my data, but how do I set up the FIFO to read in at the correct rate and out to the pin? 

 

Happy holidays 

--- Quote End ---  

You write a state machine and then control registers for the state machine. For example, here's what I have for testing SERDES channels; 

 

1) An Avalon-MM system containing a JTAG-to-Avalon-MM master, various blocks of control registers, and pattern RAM blocks. 

 

2) The pattern RAM is dual ported; with one side having an Avalon-MM slave interface, the other side connects to the serializer state machine. 

 

3) The serializer state machine reads a word from SRAM and writes it to the SERDES channels. This state machine is enabled via a control register bit. 

 

You could do something similar. 

 

Cheers, 

Dave
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