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Altera_Forum
Honored Contributor I
818 Views

The Highest Carrier Frequency for Stratix III

Dears All, 

 

Greetings, 

 

I was just wondering about how high I can get as an output from the the Stratix III Development Kit as a carrier frequency. I know I can use two ways to generate that signal using (nco or .mif file for the simulated signal from Matlab), and I'm really hoping to get something close to 1GHz (for example) if it possible! 

 

Thank you for your consideration :)
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17 Replies
Altera_Forum
Honored Contributor I
83 Views

to get 1GHz carrier then you need sampling freq of 2GHz at least i.e. just output +1/-1 (no need for LUT or NCO).  

Can you get Fs of 2GHz. Certainly not in the logic fabric but may be in the serdes sections. However what do you want to do with carrier. You need to carry some signal on it(modulate). Can you do that in serdes? I doubt it. 

For such high sinusoid you need to find solutions from RF people.
Altera_Forum
Honored Contributor I
83 Views

Thank you for fast reply Kaz ... Yes, I have a signal to be up-converted inside the FPGA. I don't know about serdes, if it possible or not!  

 

now my question is how high frequency,roughly, I can get from (LUT or NCO) as a carrier frequency. I tried to make the up conversion in Matlab and just store it at the LUT but I realized that I'm having different frequency from the HSMC output.. so I started to wonder about how high I can get!
Altera_Forum
Honored Contributor I
83 Views

It depends only on your Fs (clock). The highest sine frequency for on given clock is half of that clock i.e. when you sample only two data points per sine cyle from LUT. 

Thus if you want higher freq you need higher clock(for same LUT)
Altera_Forum
Honored Contributor I
83 Views

 

--- Quote Start ---  

 

I was just wondering about how high I can get as an output from the the Stratix III Development Kit as a carrier frequency. I know I can use two ways to generate that signal using (nco or .mif file for the simulated signal from Matlab), and I'm really hoping to get something close to 1GHz (for example) if it possible! 

--- Quote End ---  

Please explain what you want the 1GHz carrier for, and we can provide some advice. For example, the carrier can be generated using an digital-to-analog converter (DAC), or an external direct digital synthesizer (DDS), or an external phase-locked loop (PLL) (with low-jitter VCO). The design depends on your jitter requirements and whether you need to program the frequency, etc.  

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
83 Views

 

--- Quote Start ---  

I have a signal to be up-converted inside the FPGA.  

 

--- Quote End ---  

What is the signal bandwidth? 

 

 

--- Quote Start ---  

 

now my question is how high frequency,roughly, I can get from (LUT or NCO) as a carrier frequency. I tried to make the up conversion in Matlab and just store it at the LUT but I realized that I'm having different frequency from the HSMC output.. so I started to wonder about how high I can get! 

--- Quote End ---  

FPGAs can be used to process samples in parallel, so the frequency of the FPGA does not have to match the frequency of the signal. I have systems that process 1GHz clock rate sampled data; inside the FPGA, the data is processed at 125MHz clock rate, with 8 samples processed every clock. I am currently testing 20GHz clock rate ADCs, where 128 samples are processed every clock at 20GHz/128 = 156.25MHz, or 64 samples are processed at twice that frequency. 

 

In the case of a narrow bandwidth signal that needs to be modulated to higher frequencies, you can use multirate sampling filters. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
83 Views

Now I get it ... Thanks for the help :)

Altera_Forum
Honored Contributor I
83 Views

Though parallel processing is an option but I doubt achieving 1GHz. You may split up signal path into 4 branches at 250MHz each but there will be dependency especially with filters and I doubt if this practical. I prefer to go as far as 300MHz clock at best thus restricting myself to about 100+MHz sinusoid including signal bandwidth.

Altera_Forum
Honored Contributor I
83 Views

Dear Dave, 

my signal bandwidth is about 100MHz ... I already have a signal generator that provides me with 3GHz carrier frequency but I just want to up convert my signal twice once inside the FPGA and twice by the signal generator.  

 

I will try to change my Fs and see how much I will get. 

 

Thanks,
Altera_Forum
Honored Contributor I
83 Views

 

--- Quote Start ---  

Though parallel processing is an option but I doubt achieving 1GHz. You may split up signal path into 4 branches at 250MHz each but there will be dependency especially with filters and I doubt if this practical. I prefer to go as far as 300MHz clock at best thus restricting myself to about 100+MHz sinusoid including signal bandwidth. 

--- Quote End ---  

Sure its practical. 

 

I have ~600 Stratix II FPGAs synchronously processing 4GHz of sampled bandwidth across 120 boards, and another ~1000 FLEX10KE FPGAs (yeah, that old) processing another 8GHz (all using 1GHz clock rate ADCs and parallel processing); see p25 of these slides (p27 of the PDF) 

 

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf

 

Not cheap, but practical :) 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
83 Views

 

--- Quote Start ---  

 

my signal bandwidth is about 100MHz ... I already have a signal generator that provides me with 3GHz carrier frequency but I just want to up convert my signal twice once inside the FPGA and twice by the signal generator.  

 

I will try to change my Fs and see how much I will get. 

 

--- Quote End ---  

You will need to convert it to an analog signal first. How do you plan on doing that? 

 

How will your signal get off the FPGA to the 3GHz carrier? How were you planing on modulating the signal; single-sideband mixer, quadrature mixer? 

 

Where does your 100MHz need to end up in analog frequency? 

 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
83 Views

For example parts that can be used to modulate your 100MHz signal, check out this previous discussion between Kaz and myself; 

 

http://www.alteraforum.com/forum/showthread.php?t=29701&page=2 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
83 Views

 

--- Quote Start ---  

Sure its practical. 

 

I have ~600 Stratix II FPGAs synchronously processing 4GHz of sampled bandwidth across 120 boards, and another ~1000 FLEX10KE FPGAs (yeah, that old) processing another 8GHz (all using 1GHz clock rate ADCs and parallel processing);  

Dave 

--- Quote End ---  

 

 

Hi Dave 

 

You may be focussed on research based work. In all the companies I worked for, we never went down anything more than one level of parallel processing of dsp path. I doubt even experienced engineer can easily manage a simple fir filter on even/odd signal paths let alone breaking signal path down further. In a commercial environment for high speed there are far better solutions than fpgas which are mainly used to lift up baseband a bit higher than dc. 

I think the post by Mohanadig suggests he is too fresh for parallel work.
Altera_Forum
Honored Contributor I
83 Views

I already have the part of mixing the signal with the 3GHz solved I had the output from the two HSMC outputs.  

 

but, I didn't really get what you mentioned about converting to analog signal first .. because the case is to have the up converted signal inside the FPGA before it is sent to the HSMC output. 

 

Thanks,
Altera_Forum
Honored Contributor I
83 Views

Hi Kaz, 

 

 

--- Quote Start ---  

 

In all the companies I worked for, we never went down anything more than one level of parallel processing of dsp path. I doubt even experienced engineer can easily manage a simple fir filter on even/odd signal paths let alone breaking signal path down further. In a commercial environment for high speed there are far better solutions than fpgas which are mainly used to lift up baseband a bit higher than dc. 

 

--- Quote End ---  

Yeah, fair enough :) 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
83 Views

 

--- Quote Start ---  

I already have the part of mixing the signal with the 3GHz solved I had the output from the two HSMC outputs.  

 

but, I didn't really get what you mentioned about converting to analog signal first .. because the case is to have the up converted signal inside the FPGA before it is sent to the HSMC output. 

 

--- Quote End ---  

The signals on the HSMC outputs are digital values. 

 

Is your 3GHz mixing logic digital (like one of the devices in the links above), or analog? 

 

If the mixing is analog, then you would need an digital-to-analog conversion (DAC) of your 100MHz bandwidth signal, where the 100MHz bandwidth signal is possibly resampled to a 500MHz clock rate, or 1GHz clock rate signal, prior to analog mixing. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
83 Views

It is analog, and I will put that in my consideration thanks for the help.

Altera_Forum
Honored Contributor I
83 Views

 

--- Quote Start ---  

It is analog, and I will put that in my consideration thanks for the help. 

--- Quote End ---  

Ok, so you will have to convert your 100MHz bandwidth HSMC data to analog. 

 

Texas Instruments is now making their ADC/DAC boards with HSMC interfaces, eg., 

 

http://focus.ti.com/docs/toolsw/folders/print/dac3484evm.html 

 

I haven't used this part, but it looks like it has the features you would need. 

 

Cheers, 

Dave
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