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I want to define instruction of multiplication,but there is a problem that I cann't solve.
the code is: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity mult is port(dataa:in std_logic_vector(31 downto 0); datab:in std_logic_vector(31 downto 0); result:out std_logic_vector(31 downto 0); reset:in std_logic:='0'; start:in std_logic:='0'; clk_en:in std_logic:='0'; clk:in std_logic); end mult; architecture behave of mult is signal rt:std_logic_vector(31 downto 0); begin rt<=dataa(15 downto 0) * datab(15 downto 0); result<=rt; end behave; please help me! thanks in advance! http://b31.photo.store.qq.com/http_imgload.cgi?/rurl4_b=b579f8b54f494fc69149a5de70a1aee96a8bb3395a15bfa223135b6ed1f66877333e0ee98fe950027efdba4f36399042461e971cccff013808067a464a918e626f13a199366ba222d1c8d503aaf9f20bd3d0defd&a=32&b=31 http://b31.photo.store.qq.com/http_imgload.cgi?/rurl4_b=b579f8b54f494fc69149a5de70a1aee9f2965158095d9394e8f9fcc35b25e9a1411ee3cb150f70930cfe80cf31fadf167c862b99da9005da91fd1ed71efad8180c6d064fb270f4db73076963dcbe583a984987c8&a=31&b=31Link Copied
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What's the issue you are running into?
Here is an example you can look at: http://www.altera.com/literature/ug/ug_nios2_custom_instruction.pdf http://www.altera.com/literature/ug/ug_custom_instruction_files.zip- Mark as New
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thank you for your suggestion,I will read it carefully.
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I am sorrow,I use the code that you give me to implement CRC custom instruction,but there is a same problem that I cann't solve.
I did all step by step follow the PDF,but when I select the CRC from the library on the life side panel of the Custrom Instruction tab,and click the ADD to add it to the Nios Processor,the error appears. thank you. http://b31.photo.store.qq.com/http_imgload.cgi?/rurl4_b=b579f8b54f494fc69149a5de70a1aee9158b4942fcdec056a28ce16f00afb29d8e64c3094609d5fcf27982de47cf11496e9e2e7eb30094ad8a1a95eb1f5db610f2e13eb99eb611d43f6b679363d86885849605cb&a=32&b=31
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