There are no Nios II CPUs with debug modules available

[Altera_Forum]

Hi, 

 I am facing this problem for over a week now, where when i try to debug as nios hardware the following error message shows up:  There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.  just to be clear: i have downloaded the respective .sof file (with jtag uart, and a level 1 debug module enable) to the target board (cyclone 3 running at 80Mhz external clock). the NIOS 2 processor has on-board ram, interval timer, PIO and a jtag uart. the clock pin on the processor is directly attached to the 80Mhz external clock pin input, and the reset pin is connected to Vcc.  here is the HW configuration:  Target Connection:  JTAG cable: automatic<currently: USB-Blaster [USB-0]>  JTAG device: automatic<the device which has the processor>  Nios II Terminal commnuication device: jtag_uart_0<stdin/stdout/stderr>  https://www.alteraforum.com/forum/attachment.php?attachmentid=7361   here is a screen shot of the processor: https://www.alteraforum.com/forum/attachment.php?attachmentid=7362   with jtagconfig -n i got this:  [NiosII EDS]$ jtagconfig -n 1) USB-Blaster [USB-0]  020F30DD EP3C25/EP4CE22  Node 19104602  Node 0C006E02  Please advice.  Thanks.

[Altera_Forum]

Is your processor running? 

Try to setup the NIOSII Hello World example and bring it to the board, if no answer comes, then your NIOS Config is not working...

[Altera_Forum]

It is a NIOSII Hello World example that i am trying.

[Altera_Forum]

And it works with "run as", but not with "debug as", or it does not work with both?

[Altera_Forum]

both run as and debug as are not working. How do i ensure the processor is running ?  

There are only two pin from the processor to connect which is the reset and clk pin, the reset is connected to vcc and the clk is connected to the external clk which is 80Mhz. (7W-80.000MBB-T as the oscillator) is there any other things i miss ?

[Altera_Forum]

--- Quote Start ---  both run as and debug as are not working. How do i ensure the processor is running ?  There are only two pin from the processor to connect which is the reset and clk pin, the reset is connected to vcc and the clk is connected to the external clk which is 80Mhz. (7W-80.000MBB-T as the oscillator) is there any other things i miss ?  --- Quote End ---    this should be the mistake.  Your CPU is in reset all the time if you put vcc to the reset!

[Altera_Forum]

I am still getting the same error ...

[Altera_Forum]

Have you made the Tutorial for the NIOSII on your board? 

I would try this, because now there are to many things that could be. if your reset is OK now?!

[Altera_Forum]

Before trying on my hardware, I have tried with the de2 board and it worked, and I have been following the same steps and I still get this error.

[Altera_Forum]

then I am out... 

SORRY!

[Altera_Forum]

--- Quote Start ---  this should be the mistake.  Your CPU is in reset all the time if you put vcc to the reset!  --- Quote End ---   Actually no. For an unknown reason, usually the reset input to a SOPC system is inverted, as shown by the name reset_n, so connecting it to vcc is the correct thing to do.  htio, are you sure you are using the correct .sof file? Don't forget that if you are in opencore evaluation mode, the result of the compiler will be written to a *_time_limited.sof file and not the usual one. Did the .sof upload occur without any error? Are you sure the FPGA isn't reset (failure in a power supply for example) and reloads another design from flash?

[Altera_Forum]

i am sure i am using the right .sof file, i have altera quartus 9.0 license (so there are no *_time_limited.sof on the folder), and also i have been doing the same thing on another cyclone 3 board (EP3C40F324C8N where my board is using EP3C25Q240C8N) and it works on that board, the architecture of the processor is simple : 

a interval timer, a on-chip memory, a jtag uart, and the processor itself.  the .sof file on both is uploaded without any error ( I even check the Config_Done pin on the fpga with a scope)  and i am running the simple hello world example from the nios 2 IDE 9.0 with the correct .ptf file loaded respectively. successfully compile for both. But error occure when run as/debug as on my board(EP3C25Q240C8N).  , so i am sure that there is nothing to do with the usb blaster, please advise... i am running out of ideals.

[Altera_Forum]

Is your clock input correct? You could redirect it to a fpga output pin and check it with a scope, to be sure the FPGA is picking it up correctly, or feed it to a PLL and check the pll's "locked" output with Signaltap. 

What does Timequest say? Does your design meet all the timing requirements and are all the paths correctly constrained? If you go into System Console and scan the JTAG chain, do you see the Nios CPU and the JTAG UART in the connections tree?

[Altera_Forum]

the clock input are correct as i have check it with a scope and other nomal logic code works. 

there are warnings: https://www.alteraforum.com/forum/attachment.php?attachmentid=7389  and https://www.alteraforum.com/forum/attachment.php?attachmentid=7390   as for the Jtag: with  jtagconfig -n i got this:  [NiosII EDS]$ jtagconfig -n 1) USB-Blaster [USB-0] 020F30DD EP3C25/EP4CE22 Node 19104602 Node 0C006E02

[Altera_Forum]

Hi, i got it work by using this command line: 

nios2-download -g hello_world_1.elf && nios2-terminal  /cygdrive/d/niostest/hello_world_1/hello_world_1/Debug [NiosII EDS]$ nios2-download -g hello_world_1.elf && nios2-terminal Using cable "USB-Blaster [USB-0]", device 1, instance 0x02 Pausing target processor: OK Initializing CPU cache (if present) OK Downloaded 20KB in 0.3s (66.6KB/s) Verified OK Starting processor at address 0x000081C8 nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 2 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)   hehehaha Nios II!    But when i use Debug as (on the Nios2 9.0 IDE) it shows the same error: There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.

[Altera_Forum]

Hmmm there seems to be a communication error between the IDE and Altera's JTAG server... unfortunately it means you'll probably have to keep using the command line tools.

[Altera_Forum]

its kinna hard for me to debug ...