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Thesis Topic

Altera_Forum
Honored Contributor II
712 Views

Hi people, 

 

I am a new bie to this forum and I am a graduate student, in need of a masters thesis project on Altera FPGA board. 

My professor had asked me to check the possibility of modifying the NIOS ii core (32 bit) by adding some instructions so that an arbitrary precision 

integer arithmetic library can be implemented. An application is, using that library we can implement an RSA encryption scheme. 

 

I understand that it is possible to add custom instructions to the NIOS ii core and I see the tutorial link in the altera website. 

 

Kindly help me here and let me know if I am going in a proper direction (one question I have in my mind is in any vhdl/verilog code, we can make a register 

variable which can be of any number of bit size, which depends on how we define it. Even if the synthesized code may not go and fit onto a board, we still can have 

simulations on the modelsim from the same module. So does it really make a good sense if I say an arbitrary precision implementation on an FPGA). 

I am stuck at this thought, please advice me. 

 

Any comments / eye openers are quite appreciated. 

 

Thank You, 

Akhil
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1 Reply
Altera_Forum
Honored Contributor II
71 Views

Custom instructions are one method and memory mapped accelerators are another. When the accelerator can operate quickly and contains few inputs custom instructions make sense to use. When there is a block of data to compute then a MM accelerator (sometimes with a DMA) makes more sense to use. One thing to keep in mind is that custom instructions block the processor pipeline. 

 

So you have plenty of options but you should estimate computation times and input data sizes before choosing an accelerator method.
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