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Altera_Forum
Honored Contributor I
1,067 Views

Time-limited OpenCore Plus cores problem

Hi,  

I am new to nios2.I am using cyclone 2 fpga starter board ( I am using Quartus2 web edition ).I have tried design example given in the manual of nios2.I was able to complie and simulate my design but when I tried to program my design in fpga, i am getting error like this. 

 

Info: SRAM Object File C:/Thesis/nios/niosII_hw_dev_tutorial/nios2_quartus2_project_time_limited.sof contains time-limited megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x00A2 

Info: Started Programmer operation at Thu Oct 27 14:23:34 2011 

Info: Configuring device index 1 

Info: Device 1 contains JTAG ID code 0x020B30DD 

Info: Configuration succeeded -- 1 device(s) configured 

Info: Successfully performed operation(s) 

Info: Ended Programmer operation at Thu Oct 27 14:23:36 2011 

error: can't communicate with device. device will stop functioning when it reaches its non-tethered mode timeout limit. 

 

 

does anyone have solution for my problem?
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6 Replies
Altera_Forum
Honored Contributor I
66 Views

Does that error occur immediately after you download using the Quartus programmer? The tools are telling you that you need to keep the programming cable connected as well leave the nag message that pops up on the screen otherwise the hardware will timeout and stop operating. 

 

If the Nios II core is the only thing in your system requiring a license then you could work around this by switching the cpu to the 'e' core. The e core doesn't require a license and as a result will not cause Quartus II to generate the time limited .sof file. The performance of the 'e' core is much lower than the 'f' core due to the lack of caches and pipeline.
Altera_Forum
Honored Contributor I
66 Views

Thank you for your reply, 

 

Yes,That error occered immmediatly after my download. 

 

I have tried with 'e' core, but still I am getting the same message. 

 

I am using JTAG core, Timer, system id peripheral,PIO and onchip memory for my design.I am just trying the design example given in the manual, but for my project I have to add more components ( I am a student, I cannot afford licences :( ).
Altera_Forum
Honored Contributor I
66 Views

When you switched to the 'e' core there should have been a non-time limited .sof file generated. Sort your directory by file type and make sure there isn't a more recent .sof file that isn't time limited. 

 

What are you using to download the .sof file? The Quartus II programmer or configure-sof from the command line? If it is the latter try the QII programmer instead since I'm not sure how the nag message is supposed to behave if you download using the command line.
Altera_Forum
Honored Contributor I
66 Views

Hi, 

Thank you very much. you saved my life :).It is working after changing the processor type to nios 'e'. I was able to flash my processor design to FPGA chip but the bad thing is I cannot flash my c code into the nios processor system.I have compiled the code and when I tried to run it as nios2 hardware,I can see the jtag connected in target connections tab but I am getting error message "connected system ID hash not found on target at expected base address". 

 

I tried with ignoring mismatched system id (I have searched about this error in forum and one guy sugested to do so) but I am getting one more error "Downloading ELF Process failed". 

 

Do you have any idea about this error. 

 

Thank you in advance 

Sarat
Altera_Forum
Honored Contributor I
66 Views

Perhaps the flash programmer is downloading the wrong .sof file. If you haven't already done so I would delete the old time limited .sof file just in case.

Altera_Forum
Honored Contributor I
66 Views

Hi, 

 

Thank you for your help.My problem was solved.There was some problem with my previous fpga board. Now I am using DE0 Nano, I was able to run the program. 

 

regards, 

Sarat
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