Timing failure in the SDRAM of the NIOS Simple Socket Server

[APaga1]

Hello,

            I am trying to use NIOS II Simple Socket Server design template where I have integrated our custom IP in the ethernet standard main system qsys file. When we are trying to compile, we are getting timing violations in the SDRAM that is present in the ethernet standard main system qsys. As this is something from the Intel, I am unable to interpret the nodes that I have located through the Timing analyzer GUI. I have used afi_clock as input clocks to our customized IP that I have integrated with NIOS. Kindly help. I am attaching some screenshots. The board that we are using is Cyclone V GT. 

[APaga1]

Can someone please help me with this as this is an important task that is pending for a long time?

[BoonBengT_Intel]

Hi @APaga1,

Thank you for posting in Intel community forum, apologies for the hold and hope you are doing well.
Would suggest that perhaps you can start with "Tools --> Advisors --> Timing Optimization Advisor --> Maximum Frequency (fmax)" in Quartus. There details of the issues description, recommendation followed by actions.

If you still have timing violations after doing the basic things to improve fmax, then you might need to restructure your SOPC Builder system (for example, put some of the slaves on a bridge so that not everything is on one big Avalon bus).

Note: further details of those constraints and optimization can be found in the following document here.

Warm regards.

[BoonBengT_Intel]

Hi @APaga1,

Hope this message find you well and good day, as we do not receive any response from you to the previous clarification that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 

Warm Regards