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Altera_Forum
Honored Contributor I
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Timing problem

Hello every body; 

I have a pipelined custom component that have a fixed latency, I made a Nios c code to access this component directly through its base address ,this component work with the same clk that operates the Nios. 

How many clks it takes to write to, or read from this component if I used the simple Iowrite and Ioread instructions. 

Thanks.
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